Research On ADMM-based Decoding Method For Binary LDPC Codes And FPGA Implementation

As a Shannon-limit approaching coding technique,Low-Density Parity-Check(LDPC)codes have been widely used in various communication systems.Because FPGA has the characteristics of programmable and high-speed operation,research on the design of LDPC decoder based on FPGA platform has become an important realization method of LDPC decoding.The linear programming(LP)decoding algorithm is a new type of decoding method which has received extensive attention in recent years and has a lower error platform than the traditional Belief Propagation(BP)decoding algorithm.In this thesis,a decoding algorithm for Alternating Direction Method of Multipliers(ADMM)based on the minimum polyhedron with penalty function is studied for the LP decoding method of binary LDPC codes.The main content of this thesis is as follows: 1.The basic concepts and related basic knowledge of LDPC codes are introduced,and the basic principle of BP decoding algorithm is given.Based on the Maximum Likelihood(ML)decoding algorithm,the relaxation method of LP decoding is discussed,and the Feldman LP decoding model is given.And the basic principle and iteration framework of the ADMM algorithm are discussed.2.Combining the minimal polyhedron model and the ADMM algorithm,an LP decoding algorithm based on the minimum polyhedron model and the ADMM technique is presented.The algorithm effectively reduces the complexity of the decoding model by the checking node degree decomposition technology,and the designed decoder does not need to invoke the projection algorithm,which further reduces the complexity of the decoder,and the algorithm can be executed in parallel.Combining the penalty function and the LP decoding algorithm based on the minimum polyhedron model and the ADMM technique,an ADMM decoding algorithm based on the minimum polyhedron with penalty function is presented,which effectively improves the decoding performance of the algorithm.3.Aiming at the ADMM decoding algorithm based on the minimum polyhedron with penalty function,a partial parallel structure LDPC decoder design method is proposed.Making full use of the internal structure of the LP decoding model,we simplify complex matrix multiplication operations into addition operations between non-zero elements.And according to the structural characteristics of the matrix in the decoding algorithm,the storage of information is optimized,which saves storage resources and improves the decoding speed.4.The above-mentioned LDPC decoder based on ADMM algorithm is designed on the Xilinx Virtex-6 FPGA platform.The test results show that the LDPC decoder designed in this thesis works well and can realizes correct decoding of LDPC codes.