K/Ku Band Broadband Signal Source Based On DDS And PLL

With the rapid development of military radar and wideband transceivers,the high performance is required for signal sources in these application systems.Wide operation band,low spurious,low phase noise,fast agile frequency have gradually become the research trend of signal sources.In this paper,a low phase noise,low spurious and high frequency resolution signal source with output frequency of 16.5~25.0 GHz is developed by utilizing direct digital frequency synthesis(DDS)technology and phase locked loop(PLL)technology.The signal source,in which the frequency division ratio allocation of the PLL is optimized,uses a low additional phase noise phase detector chip to assure low phase noise performance.The main contents of this paper are as follows:(1)The main schemes of frequency synthesis technology for broadband sweeping signal source is discussed.The advantages and disadvantages of direct frequency synthesizers,DDS,simple PLL synthesizers and PLL synthesizers excited by DDS are compared in principle.According to the performance requirements of broadband,low spurious,low phase noise and fast sweep,a PLL synthesizer excited by DDS is chosen in this work due to high frequency resolution of DDSs and high spurious suppression in PLL synthesizers.A detailed design scheme is proposed,and key parameters are simulated and analyzed.(2)A DDS module is designed.A high-order frequency multiplier which provides high frequency reference signal for the DDS,DDS chip peripheral circuit along with its register configuration and control circuits are designed.Considering that the highest required frequency of output signal is near 800 MHz,AD9914 chip with the highest reference clock frequency of 3.5GHz produced by ADI is selected.A step recovery diode is used to design a high-order frequency multiplier.Two-stages of surface acoustic wave filters are used to suppress the spurious and harmonic components of the output signal and filter out a high-quality 3.4 GHz reference clock signal for the DDS.The measured results show that the output power of the reference clock signal at 3.4 GHz is-2.71 dBm,the phase noise is-124.83 dBc/Hz@10KHz,and the spurious suppression is higher than 50 dBc,which meets the design requirements.The control circuit of DDS frequency synthesizer is designed by using MSP430F5529 chip of TI.The registers of AD9914 chip is written by SPI communication mode to change the output signal frequency of DDS module.The measured results show that the output signal frequency range of DDS frequency synthesizer is 515.625~781.25 MHz.At 640.625 MHz,the spurious suppression is 64 dBc,the phase noise is-134 dBc/Hz@10KHz.The output power level fluctuation is around 1 dB within the full operation band.The DDS exihibits excellent performance and meets the input reference signal requirements of PLL frequency synthesizer.(3)In order to assure low phase noise,HMC439 phase-frequency detector(PFD)chip with very low figure of additional noise is chosen.HMC588 voltage controlled oscillator(VCO)chip is chosen to meet the requirement of output signal frequency range.PFD and VCO chips are not integrated with frequency dividers,so it is necessary to add an external frequency divider in the loop.PLL circuit is originally designed by using Hittite PLL Design software to simulate the resistance and capacitance of the loop filter and two quarter dividers are selected as PLL loop dividers.During debugging,it was found that the original PLL circuit has certain defacts including considerable output power fluctuation,spurious and poor phase noise performance.In order to solve these problems,some improvements have been taken in frequency division ratio configuration,VSWR characteristics of RF circuit and shielding cavity design.The improved PLL circuit is designed and manufactured.The test results show that the improved PLL circuit is superior to the original PLL circuit in spurious suppression and phase noise.The output frequency of PLL frequency synthesizer is 8.25~12.5 GHz.At 10.25 GHz,the spurious suppression is 71 dBc and the phase noise is-112 dBc/Hz@10KHz,which achieves excellent performance.(4)The operation interface of the signal source control system is designed.The operation control system based on TFT screen and keyboard is designed using C language programming.The control system can conveniently set the parameters of the single frequency and the sweep frequency output signal,which are displayed on the TFT screen.In addition,a scheme of longdistance wireless control system is proposed.Through the network communication between an application on cell phone and ESP8266 WIFI chip,long-distance and low time delay controlling is preliminarily realized,which provides a new feature for the signal source control system.(5)The required RF signal of 16.5-25.0 GHz is finally generated by feeding the PLL output signal through a frequency doubler.At 18.5 GHz,the spurious suppression is measured to be 57 dBc,the phase noise is-108 dBc/Hz@10 KHz,and the step frequency is 100 KHz.The minimum sweep period is 0.6ms and the power level fluctuation is 4.7dBc.The measured results demonstrate that the signal source designed in this work exihibits the characteristics of broadband,low spurious,low phase noise,fast sweep and high stepped frequency resolution.Electronic countermeasures and anti-jamming technologies require fast frequency conversion and high frequency broadband signal.The broadband,low spurious,fast frequency conversion and high stepped frequency resolution of the signal source designed in this paper can meet the requirements of high-performance signal generation.It has good application prospects in radar,communication or measurement instruments.