An Energy Efficient JPEG Encoder With Approximate Computing Paradigm

In recent years,with the rapid development of microelectronics and multimedia technologies,digital image compression coding technology has become more and more widely used in resource-constrained areas such as implantable medical devices,wireless sensor network devices,and miniature sensors.With limited resources,it is necessary to design a digital image compression chip which can comprehensively consider the requirements of energy efficiency,performance and image quality.This paper chooses the compression technology of the JPEG standard for digital image coding as its research object.Image compression can tolerate a certain degree of inaccurate computing.So this paper exlpores approximate computing and near-threshold computing technology in the JPEG standard coding chip for energy efficiency and performance improvement with a small amount of precision loss.On the basis of further analysis of the baseline algorithm module of JPEG standard,this paper selects the neural networks to mimic and replace computation intensive modules of the JPEG encoding algorithm.Then,based on the analysis of the hierarchical structure,data flow,weights and configuration of the neural network system,this paper designs a reconfigurable neural network accelerator with high flexibility and high performance.This accelerator is used to speed up the implementation of hardware neural network computation,which is reconfigurable for different network topology mappings.On the other hand,this paper optimizes the JPEG encoder chip from architecture level and the underlying process,so that it can operate at the near-threshold voltage region to achieve a significant reduction in power consumption while ensuring a high performance.In this paper,the SMIC40 nm process is used to comprehensively verify the JPEG encoder based on approximate computing technology.Experimental results show that with a threshold voltage of 0.6V,the minimum energy efficiency of JEPG encoder system is196.74 pJ/pixel at the maximum clock frequency of 40 MHz,supporting 480 P at 15.93 fps.Results show up to 5.0× energy reduction with 2.5× performance degradation when compared to using a 1.0V nominal supply.The energy efficient JPEG accelerator chip designed in this paper has achieved a good balance in terms of flexibility,image error,energy efficiency,performance and area compared with other low-power chips.Therefore,this study is of great significance to promote the development and application of image processing technology.