Design And Structure Investigation Of High Voltage 4H-SiC MOSFET Devices

Silicon carbide is a typical representative of the third generation of wide bandgap semiconductor materials.Due to its wide bandgap,high thermal conductivity,high electron saturation drift velocity and high critical breakdown electric field,it is especially suitable for high voltage,high frequency,and high power device manufacturing.Silicon carbide metaloxide-semiconductor field effect transistor(SiC MOSFET)have advantages such as low onresistance,fast switching speed,and high reverse voltage,which makes their application in power electronics extremely promising.Although the silicon carbide industry has developed rapidly in recent years,commercialization of 600 V,1200V and 1700 V SiC MOSFET devices has been achieved.However,on the one hand,there is no commercialization of ultra-high voltage SiC MOSFET,and there are few successful examples,on the other hand,there is still much room for optimization of SiC MOSFET structure,such as gate oxide reliability,the specific on-resistance,switching time and other parameters can be improved by optimizing the structure.Base on this,a 10 kV 4H-SiC MOSFET is designed and two optimized structure of SiC MOSFET are proposed in this papaer.The main work is concluded as follows:(1)The basic working principle of SiC MOSFET and the structural characteristics of tradition VDMOSFET are studied.The key parameters such as breakdown voltage,onresistance and threshold voltage are discussed.In particular,the on-resistance is analyzed in detail,the different calculation models of drift region are compared,and the on-resistances of each part are calculated quantitatively.The ratio of the on-resistance of each part to total onresistance at different voltage levels is analyzed.(2)The physical models for simulation of SiC MOSFET devices are studied,including incomplete ionization model of impurities,carrier generation-recombination model,impact ionization model and mobility model.The carrier mobility models are studied in detail,and several typical carrier mobility models are compared.The intrinsic scattering mechanism considered by these models is described and calibrated using the measured data of the 4SM03 series 4H-SiC MOSFET independently developed by the Institute of Microelectronics,Chinese Academy of Sciences.(3)The cell of 10 kV 4H-SiC MOSFET is first designed by Silvaco TCAD.Then,through the process simulation of Silvaco Athena,reasonalbe concentration distributions of P+,N+and Pwell are obtained,and then the sensitive parameters such as the width of the JFET region,the concentration and thickness of the current spreading layer(CSL)are optimized by Silvaco Atlas.The designed cell has a threshold voltage of 4.2V and a breakdown voltage of 15930 V.Then the termination of the device is designed and optimized in detail,the termination size is 617?m and the termination efficiency is 97%.Finally the layout of the device is designed by L-edit.(4)Two 1200 V 4H-SiC MOSFET optimized structures are proposed in this paper.One is to introduce a P-type doping in the JFET region to reduce the gate oxide field,and introduce an N-type doping in the accumulation region to enhance the current capability of the device.After optimizing the key parameters such as the concentration and the width of the extra doping,the width of the JFET region,compared with the conventional VDMOSFET,the specific onresistance is slightly increased and the gate oxide field is effectively reduced.The other is to use a split-gate structure to improve the switching characteristics of the devices.The central implant at the JFET region is used to alleviate the electric field of the poly-Si edge.The CSL structure is used to ensure the current capability of the device.After optimizing the width of the JFET region,the thickness and concentration of CSL,and the gate length,compared with the conventional VDMOSFET,the gate oxide field and the gate-to-drain charge are effectively reduced.