Design Of Exclusive-OR Gate Based On Characteristic Of Quantum-dot Cellular Automata

In the past decades,the technology of digital integrated circuits has developed rapidly.With the improvement of integrated degree and the decrease of the devices size,semiconductor devices are approving the physical limit little by little.CMOS devices are facing new realization challenges,such as high power density,crosstalk and so on,seriously impact on the development of integrated circuit.Therefore,the necessity for an alternative technology that could provide a revolutionary approach to nanoscale work seems more important than ever.Quantum dot cellular automata(QCA)is a new nano-scale digital circuit manufacturing technology.It has lower power consumption,more integrated and speed faster.It can solve the problems which are brought by the narrowing of the device size in the traditional CMOS circuits.Many virtues make it an attractive alternative to traditional CMOS technology.In QCA circuit,the method of transmitting information is different from traditional circuit.It is realized by the interaction of Coulomb forces between electrons.One cell can transmit information to other cells within the radius of influence.Based on this characteristic,QCA circuits have different design methods.In order to design circuits with low power consumption and low delay,it is necessary to evaluate several satellites for different design methods.This paper summarizes the existing QCA XOR gates,and classifies these XOR gates based on four design methods.And the XOR gate is analyzed,and the most suitable design method for XOR gate is obtained through comparative analysis.Based on the results of comparative analysis,This paper presents a novel low power Exclusive-OR gate which is mainly based on the intercellular effects method,the energy consumption is reduced by 29% compared with other optimal designs.The correctness of the circuit function is verified by calculating the electrostatic energy of the output cell.Based on the proposed XOR gate,parity checker circuit and adder circuit are implemented.The circuit is analyzed from the area,cell number and delay.It is found that the proposed parity checker is the best design compared with the previous one.For adder,it has advantages in application to low-bit adder.At the same time,D-flip-flop is designed based on the XOR gate.Compared with the previous design,the area and cell number of D-flip-flop are optimized by 50% compared with the previous best design,which has obvious advantages.The torsion ring counter is completed with the realized D-flip-flop,and the correctness of the logic function is verified in QCA Designer software.