Fabrication And Electrical Performance Of Hybrid CMOS Inverters Based On Printed Carbon Nanotube And Metal Oxide Thin Film Transistors

Printed complementary metal-oxide-semiconductor(CMOS)inverters with low power consumption and high noise immunity are important to realize practical applications of large-scale printed logic gates and circuits.Compared with traditional micro-nano process for fabricating thin film transistors(TFTs)and CMOS inverters,printing techniques have some significant advantages,including directly depositing patterns,low cost,high material utilization,flexibility,and large area.However,the performance of current printed CMOS inverters is still non-ideal because of unmatched performance of p-type and n-type TFTs.In this thesis,I focus on the preparation of high performance hybrid CMOS inverters based on printed n-type metal oxide TFTs and p-type carbon nanotube TFTs with low operating voltages.The performance of n-type metal oxide TFTs was optimized by tuning gate dielectrics materials and their thickness,and adjusting the compositions of the metal oxide inks.The best performance of the IZO TFTs were achieved when the molar ratio of In:Zn is 1:1 with gate dielectric of 50 nm HfO2.Printed chirality enriched(9,8)SWCNT TFTs were acted as p-type TFTs,which have similar electrical performance with n-type IZO TFT at low operation voltage.The resulting printed hybrid CMOS inverter with good uniformity showed excellent performance with voltage gain up to 45,noise margins of?83%at 1/2 Vdd,and low static power consumption of 0.4?W at Vdd of only 2 V under the relative low annealing temperature(300 ?).Next,printed metal oxide TFT,SWCNT TFT and CMOS inverter with ion gels as the gate dielectrics were fabricated.IO TFTs with the mobility of 6 cm2 V-1 s-1 were obtained with the operating voltage of 1 V by optimizing the composition of metal oxide ink,the printing times and the annealing temperature at atmosphere.Meanwhile,the performance of SWCNT TFT was optimized by adjusting the contact area between gate electrodes and ion gel dielectrics.The optimized p-type SWCNT TFT has the mobility of 4 m2 V-1 s-1 under voltage of 1 V.Furthermore,the first hybrid CMOS inverters based on n-type IO TFTs and p-type SWCNT TFTs which use ion gels as gate dielectrics was prepared,which has nice performance at Vdd less than 1V.