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Hardware Impletentation Of Reliability-Oriented Decoder Based On Protograph LDPC Codes

Posted on:2020-04-08Degree:MasterType:Thesis
Country:ChinaCandidate:H FuFull Text:PDF
GTID:2428330575464724Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
In 2019,5G commercials have been officially put on the agenda.The LDPC(Low Density Parity Check)codes used as the 5G data channel coding scheme has become the standard for service transmission.The protograph LDPC codes is a special subclass of the LDPC codes.The error floor of some patterns which belongs to protograph LDPC codes is extremely low,and in some environments there is even no wrong floor.In the application of practical communication system,the quality of decoder is one of the key factors that affect the performance of the system.In this paper,a reliability-oriented decoder is designed and implemented for the protograph LDPC codes.The main work of this paper is as follows:For the problem that the Reliability-wise decoding algorithm with higher performance but has higher complexity,this paper has made two innovations in algorithm simplification.Firstly,the weighted updating of the three reliability factor amplitudes is simplified into two kinds,and the simplified algorithm and the original RW-BP algorithm are compared by si,mulation.The simulation results show that the performance of the RW-BP algorithm is better than the Log-BP algorithm.Secondly,the TDMP(Turbo Decoding Message-Passing)layered decoding algorithm suitable for hardware implementation is merged with the above simplified algorithm,and the algorithm(RW-TDMP)implemented by the decoder is given.Simulations show that the algorithm maintains the performance of the original RW-BP algorithm.In the hardware implementation design,for the problem that the reliability index Sv under the partial parallel structure of RW-TDMP layered decoding algorithm cannot be updated,a compromise solution of“storing small and taking small”is proposed.The overall architecture allows for the calculation and updating of any number of reliability index magnitudes.Finally,the software and hardware simulation platform combined with FPGA and PC is built.The performance of AR4JA codes with code length of 1280 and 1/2 code rate is verified in the AWGN channel environment,which proves that the decoder design is successful.
Keywords/Search Tags:protograph LDPC codes, Reliability-wise BP, FPGA
PDF Full Text Request
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