Research On 10M/100M Ethernet PHY Verification Method Based On UVM

In recent years,with the rapid development of digital integrated circuit,research on and the development of the integrated circuit chip have become major strategic directions for national development.In the process of developing chip,design verification is very important.The verification can not only ensure the correctness of the design,but also improve the productivity of the design,and provide guarantee for shortening the period of developing chip.Although foreign productions of 10M/100 M Ethernet PHY chip have been widely used,but those Ethernet products which relates to China's security domain need to use our independently-researched and domestically-developed Ethernet kits,of which 10M/100 M Ethernet PHY Chip has to be designed by ourselves.Therefore,it is very important and challenging to verify the designing of chip efficiently and comprehensively.This article aims to verify the function of 10M/100 M the Ethernet PHY logic circuit.The 10M/100 M Ethernet PHY logic circuit verification platform needs to be established to achieve higher verification effect and better reusability.At present,most of the digital circuit design verification uses co-verification with both software and hardware,and the test stimulation is generally directional test,so it is difficult to achieve the design goal as this paper does.This paper,with the UVM verification method,deeply studies the components of the UVM verification platform,analyzes the logical circuit function of 10M/100 M Ethernet PHY,and combines the advantages of System Verilog verification language to construct the verification platform based on 10M/100 M Ethernet PHY on UVM.Upon the function of 10M/100 M Ethernet PHY logic circuit,a detailed verification strategy is formulated and a feasible validation implementation is proposed.On 10M/100 M Ethernet PHY on UVM verification platform,combination of random test and directional test being used to generate stimulation,Makefile script used to run the validation implementation,the simulation test of self-designed 10M/100 M Ethernet PHY logic circuit is completed.Under the verification platform,verification strategy and testing method designed in this paper,and the actual verification result of 10M/100 M Ethernet PHY logic ciruit is statistically as follows: functional verification coverage rate reached one hundred percent,and the overall code verification coverage rate 96.64 percent.Both coverage rates reached the requirements of the specified verification index.Simulation results show that the 10M/100 M Ethernet PHY on UVM verification platform has reusability and easy expansibility.The verification strategy and programme in this paper can verify the 10M/100 M Ethernet PHY logic ciruit automatically and efficiently.