Synchronization Algorithms Design And Implementation For IEEE 802.11ac Receivers

Nowadays Wireless LAN has a profound impact on people's lifestyle due to its convenience and speed.The IEEE 802.11ac standard has been widely used in R&D and application due to its advantages such as high data throughput rate,high spatial diversity and dense modulation.Because the synchronization technology of receiver directly affects the transmission performance of 802.11ac system,this paper focuses on the research of algorithm and circuit design of synchronization technology.In addition,this paper also designs a baseband chip for 802.11ac transmitters and receivers with 20MHz data bandwidth in single-input-single-output mode.The innovations and major research results of this article are as follows.1.A new common phase synchronization algorithm for orthogonal frequency division multiplexing systems is proposed.The current mainstream orthogonal frequency division multiplexing system phase synchronization algorithm?Armada algorithm?utilizes pilot information in data symbols.Since the number of pilots in the 802.11ac data packet is limited,the performance of the algorithm cannot be achieved.Therefore,a public phase synchronization algorithm?Wu algorithm?based on training sequences is proposed in this paper.The simulation results show that when the signal to noise ratio is 12dB,the Wu algorithm can reduce the bit error rate of the system to 10^-4,indicating that the Wu algorithm can well correct the influence of the phase offset on the system.The mean square error of phase estimation of Wu algorithm is 10%of Armada algorithm under the same signal to noise ratio,which shows that Wu algorithm has better phase estimation accuracy than Armada algorithm.In addition,Wu algorithm can be implemented in the time domain or frequency domain,and it has better flexibility in practical applications.2.The commonly used timing synchronization algorithm is improved.The timing synchronization algorithm currently applied to 802.11ac systems is a delay-related algorithm based on training sequences?S&C algorithm?.The S&C algorithm can perform timing synchronization more accurately,but its performance will be degraded at low signal to noise ratio.Therefore,this paper improves the S&C algorithm and obtains the Zq algorithm.The Zq algorithm has three improvements over the S&C algorithm:changing the delay correlation to local correlation,improving the judgment method,and reducing the storage area.In the frame synchronization operation,the simulation results show that when the signal to noise ratio is 14dB,the packet error rate of the S&C algorithm is 80%and the packet error rate of the Zq algorithm is close to zero,indicating that the Zq algorithm can detect the data packet more accurately.In the symbol synchronization operation,Zq algorithm can always detect the position of the beginning of the symbol,indicating that the Zq algorithm can meet the timing synchronization requirements of the 802.11ac system.In addition,the Zq algorithm saves hardware area compared to the S&C algorithm.3.The feasibility and performance of the commonly used carrier frequency synchronization algorithm are analyzed by simulation.The carrier frequency synchronization algorithm uses the phase information of the value of delay correlation.The simulation results show that when the signal to noise ratio is 15dB,the mean square error of coarse carrier frequency offset estimation is 10^-2,and the mean square error of fine carrier frequency offset estimation is 10^-5.It shows that the performance of this algorithm can meet the requirement of 802.11ac system carrier frequency synchronization.4.The hardware circuit of the 802.11ac receiver synchronization system was designed,implemented and tested.This article has designed the circuit of the synchronous system that meets the requirement of performance,has designed the circuit of the synchronous system by adopting the combination of parallel and pipeline structure which meets the real-time requirement of the system and saves the circuit area.After the FPGA function verification,the function of the synchronization system circuit is proved to be correct.The circuit uses38828 logic units and occupies 34%of the chip resources of the FPGA?EP4CE115F29?.5.A baseband chip for 802.11ac transmitters and receivers is designed and implemented.This paper has designed and implemented the baseband chip of 802.11ac with 20MHz data bandwidth in single-input-single-output mode.After using a 0.11?m process to perform logic synthesis,automatic placement and routing of the entire baseband system circuit,the layout of the digital part is obtained,the layout area of which is 12152000?m².After adding the analog part,the baseband chip is finally handed over to the factory for tapeout.