Research And FPGA Implementation Of Dual-band Digital Predistorter Technology

With the rapid development of communication technology,the status of wireless communication in the entire communication field has become more and more important,which has also led to continuous advancement of wireless communication technology.The current situation of multi-standard mobile communication coexistence will continue,and the wireless communication environment needs to meet the transmission requirements of various standards at the same time.In order to meet the needs of multiple standards,multi-band communication,especially the co-time dual-band communication technology has become the research focus.In order to improve the efficiency of the dual-band power amplifier,a multi-linearization scheme has been proposed,in which the digital pre-distortion technology is widely used because it is not limited by the frequency band,the digital signal is easy to implement,and more efficient and convenient.Therefore,this paper chooses the co-time dual-band digital pre-distortion technology as the way of power amplifier linearization and research.In this paper,the design and implementation of the dual-band digital pre-distortion technology on FPGA(Field Programmable Gate Array)is studied,including the realization and optimization of predistorter,the realization and optimization of coefficient estimation,and further discussion on the influence of predistorter and The main factor of the coefficient estimation performance,and finally the performance test results.The main research contents and innovations of this paper are as follows:In the FPGA implementation of dual-band predistorter,a dual-band symmetric shared lookup table and FIR(FiniteI Impulse Response)filter series structure are proposed.The traditional synchronic dual-band digital predistorter implementation is divided according to the frequency band,and the dual frequency model requires two independent predistorter modules.In order to reduce the consumption of hardware resources,combined with the characteristics of the 2D-SRBMP(Square-Root-Based Memory Polynomial)model,a dual-band symmetric shared lookup table structure is used,that is,in the dual-band predistorter,the two input values are first stepped.The result is the index of the lookup table and the result of the lookup is shared by both bands.The lookup table output value is multiplied by the input value of the band to be the input value of the FIR filter,and the predistorter coefficient is the filter coefficient.In the FIR filter structure,the memory items are generated by the current time input value delay,which minimizes the amount of calculation.The predistorter output value is compared with the PC simulation output value.NMSE(Normalized Mean Square Error)is about-65.7 dB,which is consistent with the software simulation results.In the 10MHz bandwidth dual-band signal test,its low-band ACPR(The Adjacent Channel Power Ratio)value is around-53 dB,and the high frequency band ACPR is around-54 dB.2.In the implementation of coefficient estimation,the extended memory direct memory access combined with the FPGA logic resource acceleration scheme is used.Since the coefficient estimation is computationally complex and has obvious sequential execution characteristics,this part of the program is completed by the soft core processor of the FPGA.The processor structure is suitable for running sequential execution programs,but it is not suitable for a large number of repeated operations.Considering the logic operation capability of the FPGA,the repeated operations are moved to the logic end of the FPGA for execution.Through hardware acceleration,the coefficient estimation speed is increased several times.Compared with the coefficient estimation of the single-frequency predistorter,the coefficient estimation of each frequency band of the dual-band predistorter needs to consider the influence of two input signals at the same time.The input and output characteristics of the power amplifier model also extend from one-dimensional to two-dimensional.In the coefficient estimation,more sampling points are needed to traverse the two-dimensional input and output characteristics of the power amplifier.The test results show that at least 10K points are needed when the signal bandwidth exceeds 10MHz to achieve better pre-distortion effect,and the increase of sampling points helps to improve the system pre-distortion performance.In this experiment,by extending the external memory,it is possible to use more sampling points for the coefficient extraction module,and expand the memory read bit width through Direct Memory Access(DMA)to break through the FPGA soft core processor data bus.Bit width bottleneck.The test results show that when the input and output sampling points of the dual-band predistorter are 10K points,the coefficient estimation time is reduced from 36s using hardware acceleration to 2.5 after using FPGA logic resources acceleration.