Research And Implementation Of Digital Pre-distortion Algorithm With Feedback Structure Based On FPGA

With the increasing demand for wireless mobile communication systems,the non-linear characteristics of power amplifiers designed to match them are more complex.For the power amplifier with high complexity,this thesis studied a new digital pre-distortion algorithm with lower complexity and higher performance.What's more,this thesis proposes a design scheme of FPGA for the new algorithm.Based on researching the pre-distortion technology of power amplifier,a digital pre-distortion algorithm model based on feedback structure was proposed in this thesis.The new algorithm model introduces the previous output information and cross-terms,which are derived from Volterra series.The number of coefficients can be significantly reduced by replacing the input information polynomial with the output information of the past.In addition,the accuracy of this new algorithm model will be improved by introducing the cross terms of current input information and past output information.The experimental data show that the new digital pre-distortion algorithm model has advantages over the memory polynomial model and the generalized memory polynomial model in the complexity of the algorithm and the adjacent channel power ratio(ACPR)for power amplifiers with complex non-linear characteristics.According to this new digital pre-distortion algorithm model,the corresponding FPGA architecture was proposed.FPGA is widely used in digital pre-distortion technology because of its programmability,low cost,high speed and other advantages.Therefore,the laboratory often uses the FPGA to do engineering verification.In this thesis,feedback structure is introduced into the architecture of the FPGA.The modulus square of the signal is used as the address information to construct the lookup table,so as to save hardware resources.Finally,a simulation test platform was established to simulate and verify the performance of this new digital pre-distortion algorithm and the architecture of FPGA.The test results show that the ACPR of the new digital predistortion algorithm and the architecture of the FPGA are lower than-45dBc.