Optimal Design Of Hardware Implementation Of Blind Identification And Compensation Algorithm For The Nonlinear Distortion

As the communication environment getting more and more complex,we put forward higher requirements on the performance of the receiver.Wideband digital receiver technology has received more attention.However,the nonlinear distortion caused by the receiver will seriously affect the quality of the received signal.The method based on system identification has become an important research direction.The main idea of the method is to use digital signal processing algorithms to suppress nonlinear distortion.The engineering implementation of digital signal processing algorithm is dependent on the support of various kinds of hardware circuits.The circuit structure of FPGA is relatively flexible,which can be used for the control of some complex logic.DSP can be used for the implementation of complex mathematic operation.These two chips are the most commonly used in digital signal processing.The main purpose of this paper is to eliminate the nonlinear distortion of the actual receiver by optimizing the hardware design.In the case where the characteristic in time and frequency domains of the received signal is unknown,this paper uses blind identification and compensation algorithm for the nonlinear distortion.Before designing the specific scheme of hardware implementation,the influence of many factors on the stability of the implementation is analyzed.The first step of stable implementation of the algorithm is to get the fixed-point algorithm.Firstly,the paper considers the fixed-point scheme from the effect of the algorithm and the consumption of hardware resources.And on this basis,the calibration results of the specific fixed-point algorithm are given.After the specific fixed-point scheme is determined,the optimal design of the fixed-point multiplication unit and the fixed-point division unit in the DSP is given.In the hardware implementation part of FPGA,the logic control circuit of the main module is optimally designed.The unique influence of timing problem is also analyzed.After introducing the basic timing model,the optimal design of the key timing module is proposed.Finally,in order to verify the processing effect of the hardware system,the frame control circuit is optimized.The mixed transmission of different rate data is realized.At the same time,the continuous transmission of channelization data is completed.