Design And Implementation Of Stochastic RPC Decoder

Random Projection Code has good application prospect in adaptive rate transmission,but its decoding process includes lots of convolution operations,making it difficult to design high-speed decoder,thus hindering its application in high-speed environment.In this paper,we combine stochastic computing and belief propagation decoding algorithm of RPC to design and implement a fully parallel stochastic RPC decoder.The decoder converts the probability into a bit stream,multiplication/addition into AND/OR operation of bit streams,thus reducing the consumption of a single node.Moreover,only one signal line is needed to transmit serial bit stream between the nodes,which reduces the circuit wiring consumption,so that the circuit can operate at a higher frequency clock.Based on the basic principles of RPC codec and stochastic computing,this paper uses the Virtex-6 LX760 FPGA as the hardware platform and designs the stochastic RPC decoder with the measurement matrix whose size is 400×400 and the weight set W(28){?1,?2,?4,?4}.In the decoder,the addition in the check node is realized by using the OR gate.Therefore,the precision of the check node is improved and the complexity of the check node is greatly reduced.The preprocessing unit based on the cumulative structure is designed to keep mutual exclusion between noise bit streams,making the normalization result of the variable node's input information more accurate.The noise power scaling technology is used to further ease the latch problem of the variable node and improve the BER performance of the decoder.Reconfigurable variable node is designed so that the decoder can accommodate channel condition changes for adaptive rate transmission.In addition,a check node design scheme based on matrix splitting is proposed,which reduces the consumption of LUTs by 66.8% and the consumption of Registers by 38.2%.After completing the specific design of the decoder,the performance of the decoder has been tested and simulated.The decoder achieves a clock rate of 181.159 MHz and a throughput of about 85.3Mbps.The spectral efficiency of the decoder is close to the belief propagation algorithm,even superior to the latter when SNR<12.7dB.The decoder occupies less than 30% of the LUT,Register,and IO ports available on the FPGA.These results fully show that the stochastic RPC decoder has a high application potential.