Research And Implementation Of NTT Processor

In recent years,with the rapid development of the Internet of Things and artificial intelligence,large-scale data make the algorithm more dependent on highperformance computing.However,large-scale design models and computing resources can only be deployed in the cloud,and the high-performance and low-power intelligent chips on the mobile are needed to improve system scalability and applicability.With the constant iterative updating of the integrated circuit manufacturing process,the chip design needs to be more reusable and configurable.Fast Fourier Transform has been integrated into most specialized processors and is widely used in signal systems,speech recognition and image processing.Number theoretic transform have been used in convolutional acceleration due to their special properties.In computer systems,most Fourier transforms are performed on complex numbers and are not suitable for use in a particular area due to rounding errors.Fast number theory transform not only can effectively make up for the shortcomings caused by the approximate calculation,but also can be efficiently implemented in hardware.In addition,fast polynomial multiplication over the ring can also be achieved by number theoretic transformations.Based on the fast number theory transform algorithm,this paper studies modular reduction,modular multiplication and convolution algorithm,and designs a new NTT processor architecture on FPGA.The main contribution is as follows:The correctness of the algorithm is proved in theory,and the feasibility of the algorithm is verified by simulation.The new modular reduction algorithm can not only balance the space and time complexity on hardware,but also reduce resource utilization and improve parameter variability through dynamic and iterative operation on performance.The parameter space of the fast number theory transformation is calculated from the basic number theory,and the twiddle factor and the address generation method are improved.This paper describes the design and implementation of multi-ported RAM,and discuss the application advantages and disadvantages.According to the proposed modulo algorithm,the modular arithmetic unit under NTT processor is designed and the structure of the existing Butterfly arithmetic unit is improved to optimize the calculation process of NTT algorithm.Based on the multi-ported RAM and the improved Butterfly operation unit,a new hardware architecture of NTT processor is designed.It not only can use multiple Butterfly operation units to balance the performance of system design,but also can use the unified structure Perform forward and reverse transformation.Each module is simulated by Model Sim,and the performance analysis and evaluation are made after the function verification.In the Xilinx XUPV5-LX110 T Board hardware platform,this paper verifies the correctness of multi-ported RAM,the module modulo reduction and improved Butterfly arithmetic unit.Then PC communicated with the NTT processor through the UART interface and verified the feasibility of the proposed architecture under the custom communication protocol.