Research And Implementation Of Fault-tolerant Reinforcement Technology For Microprocessor

With the increasing integration of integrated circuits,the decreasing power supply,and the increasing speed of switch signal,the signal integrity problems that integrated circuit faces are increasingly serious,especially the signal Integrity problems caused by soft errors.Inter-line crosstalk,ground bounce,external radiation and so may lead to unpredictable soft errors within the chip,seriously affecting the system reliability and security.In the space environment,due to the existence of a large number of high-energy particle radiation,a variety of single-particle effects(SEE)happen within the chip,and the device soft error rate(SER)significantly increases.The most fundamental solution is to adopt special material or process,but the cost is too high and only applicable for national defense and military.In order to solve the above problems,this paper takes a 8051 microprocessor as the research prototype,and the soft error caused by SEE as the research object.By analyzing the soft error generation mechanism and combining the specific circuit structure of the microprocessor,the paper has studied the fault-tolerant technologies of microprocessor under deep submicron process in RTL level.The Improved Spatial-Temporal Double Module Redundancy(IST-DMR)technology is proposed for the shortcomings of the traditional redundant technology.Compared with the traditional TMR technology,the IST-DMR technology has the advantages of less overhead and better performance.This paper studies the principle and algorithm of Error Detection and Correcting(EDAC),and proposes the Extended Hamming code EDAC technology with refresh function in order to make up the deficiency of ordinary Hamming code error correction.It can detect and correct a single-bit upset of storage cel,and detect most of the multi-bit upset,and prevent error accumulation.This paper Fully studies the principle and algorithm of Berger codes,and improves Berger code error detection by detecting the code weight's parity of operands and result for error detection,greatly simplifies the circuit structure of Berger code detection and implementation difficulty.The area overhead of the MCU after reinforcement is 15.5%,and the delay overhead is 7.14%.Then this paper presents an operational fault injection method based on simulation,The experiment results show that the average failure rate of the fault-tolerant MCU dropped from 82.49% in 12.35%,with nearly 100% of the protection against the typical SET or SEU.The final fault-tolerant microprocessor taped out after the digital back-end process,using SMIC 180 nm process.All the work provides a reference and experience for the development of high reliability microprocessor.