Designs Of A Multibit Delta-Sigma ADC Using Global Chopping

With the rapid development of digital integrated circuit design,the ADC's role as a bridge for the conversion of analog signals and digital signals is particularly important for digital circuits.Among them,?-?(Delta-Sigma)ADCs are favored in low frequency measurement,audio and other fields because of their high precision,low analog circuit design complexity,and good compatibility with digital circuits.In particular,dc offset,1/f noise reduce,and accuracy improve have been the focus of research in this field.This paper first introduces the research background of ?-? ADC,and analyzes and summarizes it based on the development status at home and abroad.Then the principle of delta-sigma modulator,multi-bit quantization technology,dynamic component matching,digital decimation filter and global chopping technique are analyzed in detail.After analyzing the behavioral model system transfer function,a modulator,4-order 4-bit quantization,improved CIFF(Cascaded Integrators Feed-Forward)structure,has been established and to consider the non-linear effects feedback DAC,digital weighted average(DWA)established;With the design of the modulator,the behavioral level model of the digital decimation filter has been establish.The behavioral simulation of the complete ?-? ADC is performed to ensure the stability of the system and obtain the indicators of subsequent circuit design.On this basis,the modulator is designed on switching capacitor-based circuit,wherein the correction module DWA as a digital modulator is implemented by the RTL code;direct digital filter cascaded integrator comb of five filter(CIC filter),the output is a 24-bit digital code;Global chopping technology is implemented in conjunction with analog modulators and digital filters.The pre-stage chopper switch uses a CMOS structure with a virtual tube,and the post-stage chopper is implemented using a digital circuit.Simulation results show that with a sampling frequency of 38.4 k Hz,the signal bandwidth can be adjusted from 75 to 1.2 k Hz.The overall SNDR of the overall ADC can be as high as 123.6 d B,the effective number of bits is 20.4 bits,and the harmonic distortion is about-130 d B.The 350 nm CMOS process of Hua Hong was used to complete the layout design of the overall ADC.The simulation module used a full-custom design method.The digital part generated the layout through an integrated automatic layout and wiring.The overall layout core area was 2mm×0.8mm.After the modulator module was simulated,the SNDR achieved by the modulator was 120.4 d B,and the third harmonic distortion was-115 d B,which reached the design index.