Realization And Parallel Design Of Predicton Mode Of HEVC Video Encoder For BWDSP Platform

With the development of video technologies and applications,especially the rise of high-definition(HD),ultra-high definition(UHD),3D,and multi-view video technologies,the amount of video data generated has dramatically increased despite the network bandwidth in recent years.The transmission capacity has increased rapidly,but it is still far from meeting the requirements for the transmission and storage of massive amounts of video data.The latest video encoding international standard,High Efficiency Video Coding(HEVC),was officially released in April 2013 by the ITU-T and ISO/IEC Joint Video Collaboration Group(JCT-VC),which is mainly aimed at high-definition video.Applications.As an alternative to the H.264/AVC standard,HEVC maintains the same video quality,the code rate is only about 50%of H.264/AVC,and it also brings about a dramatic increase in algorithm complexity.Based on the actual needs of the project,this paper transplants the open source encoder software x265 that complies with the HEVC coding standard to the vector processor BWDSP1041 platform.The goal is to achieve real-time encoding and to evaluate the computing power,IO throughput,and the lowest clock frequency operation that the Soulcore DSP must have..The main task of this paper is to compile the rate-distortion cost calculation process for optimizing intra prediction.The purpose of the optimization is to maximize the use of the hardware resources of the BWDSP1041 to increase the parallelism and IO throughput of data processing.The optimization methods mainly include instruction parallelization,loop unwinding,and software streaming.These three methods are used to propose a parallel design method for functions.In the intra coding mode,the main time-consuming is in the process of recursive rate-distortion cost,when the intra-prediction selects the optimal mode,the encoder needs to calculate and compare 35 types of prediction modes RDcost,which has a huge amount of calculation.Among them,the complex and time-consuming angle model prediction and the Hadamard Transform(SATD)are designed in parallel to reduce the prediction time of the intra prediction,which is of great significance to the real-time performance of video code.This paper studies the HEVC video coding algorithm based on the BWDSP platform,and focuses on the intra prediction algorithm.This article first summarizes the key technologies in HEVC and the architecture of BWDSP processor.Then it deeply discusses the intra-frame prediction algorithm in HE VC and optimizes the correlation function based on BWDSP to calculate the intra-frame prediction rate distortion cost.The main work and innovation in this paper The point is as follows:1.Aiming at the characteristics of HEVC intra-prediction angle mode algorithm,combined with hardware resources,a parallelization method for achieving angle prediction mode computation is proposed.This method analyzes the parallelism of the angle pattern algorithm and designs a data distribution method suitable for parallel computing of multiple multipliers.Combined with the hardware resources carried by the BWDSP 1041 processor,the algorithm program for parallel operation of multiple arithmetic components is implemented.The experimental results show that the parallelism of the angle prediction mode 20 and the vertical mode 26 is realized,and the single-core parallel acceleration ratio reaches 161.68 and 344.65,respectively.2.Based on the characteristics of SATD rate-distortion cost calculation,this paper proposes to use the vector SIMD(single-instruction multiple data stream)technology to design the parallelization scheme of Hadamard transform.The scheme uses a multi-adder and a multi-multiplier cooperative working mode to increase the data throughput rate of the DSP and improve the data processing speed.The experimental results show that the parallel speedup of 87.9 on single-core BWDSP 1041 proves the effectiveness of the optimization work.