Research On Network Packet Encryption Based On NetFPGA10G And Its Low Power Consumption

The development of the fifth generation of mobile communication system,as well as the application of personal cloud computing and the Internet of Things,put forward more requirements on the functions and performance of the next generation communication network architecture.The application of more and more personal cloud services poses new challenges to network security.The traditional software-based network encryption methods are not good enough to meet the requirements of next-generation network systems for transmission rates.Meanwhile,due to the development of the Internet of Things,there are more and more network terminals,which make the research on low power consumption of network node play an important role in the realization of green network.Based on the above background,this paper used hardware encryption algorithm to achieve high-speed network packet encryption system design in Net FPGA 10 G.At the same time,the paper compared different encryption methods and different hardware optimization methods for power consumption Analyze and optimize.Finally the paper studied the low-power design method of the hardware implementation of the algorithm from different aspects.The main work and contributions of this thesis include:In the field of high-speed network security communication,this thesis studied the principle,hardware implementation and security of AES encryption algorithm and Present algorithm.Then it used the lightweight encryption algorithm Present to encrypt the network data packet.The Verilog HDL language is used to implement the algorithm in hardware.Under the framework of Open Flow switch,the high-speed AXI bus is used to connect the algorithm and Net FPGA project.The high-speed network packet encryption system with a data throughput of 10 Gbit is realized by the optimized pipeline architecture.This system helps to increase the current rate and performance of software-encrypted network packets and has been successfully applied in the EU INPUT project.In the aspect of low power hardware implementation and optimization,the hardware and software design of FPGA-based power measurement platform is completed and used for power analysis of the circuit,Based on the research of low-power methods of digital integrated circuits at the algorithm level,system level and RTL level.A method of optimizing AES encryption at the algorithm level was proposed.Power consumption of the algorithm circuit before and after optimization was measured by power consumption measurement platform.The logic resource consumption decreased by 11% and power consumption by 5% compared with that before optimization.The current algorithm is optimized for power consumption at the hardware level,which proves that the power consumption can be reduced by 20%-30% in a certain usage scenario.By comparing the power consumption of different algorithms and circuits with different structures,using the actual measurement data analysis Relevant work and conclusion have been used in the actual project,at the same time won the national Grand Prize results in the Seventh University IC competition.