The Design Of Congestion Control Circuit Module In Network Processor

With the rapid growth of network traffic and network data flow,the problem of network congestion is gradually emerging.The traditional network congestion control mechanism adopts the "tail drop" scheme,which leads to high packet loss rate.In this thesis,a congestion control hardware implementation based on weighted random early detection(WRED)algorithm and custom queuing(CQ)algorithm is proposed to reduce the packet loss rate.We first analyze and compare various congestion avoidance algorithms and congestion management algorithms,and improve the WRED algorithm used in this thesis.Then,a hardware architecture of the congestion control circuit module in the network processor is proposed,and the hardware module is divided.The congestion control circuit module is designed by Verilog hardware description language(HDL).Finally,the design is verifed by function simulation,FPGA board level verification and logic synthesis.The congestion control hardware implementation scheme based on WRED algorithm and CQ queue algorithm proposed in this thesis has a smaller packet loss rate than the usual "tail drop"congestion control scheme.Experiments show that the packet loss rate is less than 0.1%,and the integrated clock frequency of SMIC 65nm process library reaches 200 MHz.In this thesis,the design of the network congestion control circuit module can be applied to the corresponding network processor,in order to improve the network congestion situation and improve the transmission performance of the network effect.