Research On Test Vector Compression Methods Based On Vector Decomposition

Advances in process technology have resulted in a very large density of integration allowing the design of systems containing millions of transistors on a single chip.This increase in integration density has resulted in a tremendous increase in the test data volume needed to test the chips.The large test data volume not only increases the testing time but may also exceed the tester memory capacity.An effective way to reduce test data vol ume is using test compression.The goal of test data compression is to reduce the number of bits that is need ed to represent the test data.The compressed test set is stored in the tester memory and a decompression circuitry on chip is used to decompress the test data and apply it to the circuit under test.This thesis focus on test vector compression and the innovative works are as follows:(1)Test vector compression methods based on vector d ecomposition.The method decomposes an original test set to a prominent component set and a residue set.The prominent component set can be generated easily by an additional on-chip TPG,whereas the residue set can be compressed effectively and saved on the tester.When real testing is conducted,the compressed residue stored on the tester is transmitted to the CUT,and decompressed by the decompressor.At the same time,the prominent component is produced by the on-chip TPG,and then composed with the residue to restore the original test set that is at last applied to the CUT.This method can greatly improve the compression ratios o f code-based test vector compression techniques with affordable overheads.The experiment show that the average compression ratio of variable-length input huffman coding is raised from 61.02% to 81.34%,which is greatly higher than the traditional coding method.(2)Test vector compression methods based on bit reversion.The method makes it easier to compress data by reversing some bits of the test set without decreasing their fault coverage.We know that even though the fault coverage of a test set will no t change after the don't care bits are assigned value 0s or 1s,the fault coverage of some vectors that originally contain don't care bits might be increased.So,changing some specific bits in the test set may not lose the fault coverage of the entire tes t set after the don't care bits are assigned values.In order to demonstrate the effectiveness of the proposed test compression technique,we propose three general-purpose algorithms for three different classes of code-based compression methods.Experimen tal results show that the compression ratio of the three code-based schemes can be increased about 10%.If combine this method with vector decomposition,the compression rate of variable-length input huffman coding can reached to 87.98%,which is about 17% higher than traditional coding method.(3)Residue set analysis and compression.The test set with decomposing,sorting and reversion,is quite different from original test set.The number of 1s is reduced for single run length coding method.Vector decomposition halved the number of 1s in original test set,while bit reversing halves the number of 1s in residue set.By analyzing the number of 1s in each column,we know that most of the 1s in residue set are located in a few columns,and nearly half of the columns are all 0s.By removing the all zero columns,compression rate is increased by 1.23%,and final compression rate of variable-length input huffman coding has gone to 89.21%.