Research On SAR ADC For Extracting Characteristic Parameters Of Bioelectric Signals

The growing awareness of national personal health and the growing health and medical costs have driven the development of medical systems for remote monitoring and remote diagnosis of users' physical conditions.In order to obtain comprehensive and reliable monitoring information and make accurate diagnosis,it is necessary to continuously collect and quantify the physiological signals in the user's body,which requires the intelligent monitoring system to have a small physical size and extremely low power consumption.As the core module of bioelectric signal detection,ADC has great influence on the whole equipment,and as the first stage module of DSP system,if the data collected by the ADC is quantized,the characteristic parameters are extracted,and the transmission is reduced.The amount of data in the DSP processing unit can not only reduce the power consumption during data transmission,but also greatly reduce the power consumption of the DSP processing unit.Therefore,designing a low-power,highprecision ADC capable of extracting bioelectrical signal characteristic parameters is critical to the overall system.Therefore,this topic designed a 12-bit low-power SAR ADC for the extraction of characteristic parameters of bioelectric signals under the standard CMOS process of 0.13?m.Aiming at the fact that there is no large amplitude change for most of the bioelectrical signals,there is a very clear difference between the bands,and the whole signal changes periodically with time.A new type of prediction interval dynamic tracking algorithm is proposed.The algorithm greatly reduces the power consumption of the comparator and DAC capacitor array,and the results quantized based on the algorithm can be used for subsequent bioelectrical signal feature parameter extraction.Combined with the prediction algorithm and the working principle of SAR ADC,the DAC capacitor array matched with the algorithm and the overall SAR ADC architecture are designed.The feasibility of the algorithm and architecture is verified by MATLAB modeling.The area and power consumption of the DAC capacitor array is reduced by a VCM-based segmented DAC architecture.The circuit design is carried out in the Cadence environment,and the layout design was completed,and the layout is extracted.At the sampling rate of 10kS/s,the post-imitation results show that SFDR is 81.83 dB,SNDR is72.35 dB,ENOB is 11.7 bit,power consumption is 3.64 ?W at 1.2V supply voltage,and FoM value is 11.14fJ/Conv.-s.