FPGA Implementation Of Channel Estimation And Optimization Based On Wideband Micropower Wireless Communication System

As an important part of smart grid,electricity information collection system plays a vital role in the construction of smart grid.With the gradual upgrade of the business requirements of the electricity information collection system,the traditional narrow-band,low-rate micropower has been difficult to meet the expanding business requirements.Broadband micropower technology is a high-speed wireless communication network that realizes the convergence,transmission and interaction of low-voltage power users' electricity information,so it has become an ideal wireless communication solution.Due to the complex power wireless communication environment,there are various problems that affect the performance of the system such as multipath effect and environmental noise.Consedring that,fter in-depth research on the characteristics of Chirp-BOK system,channel estimation and equalization technology,the thesis proposes a channel estimation and equalization algorithm and FPGA implementation scheme suitable for broadband micropower systems.Aiming at the broadband micropower wireless communication system with preamble structure,this thesis proposes a least squares channel estimation algorithm combined with wavelet denoising.Considering the channel characteristics of the broadband micropower system,the algorithm selects Haar wavelet basis function and threshold selection criteria.In the wavelet denoising algorithm,the threshold is gradually compressed to solve the problem of constant deviation in the threshold function.The simulation results prove that the wavelet denoising algorithm with improved threshold function in broadband micropower systems significantly improves the performance of channel estimation.Then,this paper simulates and verifies the equalization algorithm of zero forcing and minimum mean square error,and analyzes its performance and complexity.By comparing the performance of the algorithm with the complexity of hardware implementation,the least square channel estimation algorithm combined with wavelet denoising and the zero-forcing channel equalization algorithm are finally selected.The fixed-point word length of the channel estimation and equalization module implemented by the fixed-point FPGA is set to 12 bits.For the hardware implementation part,this thesis designs the hardware implementation structure of the channel estimation and equalization module including four parts: preamble extraction,wavelet denoising,channel estimation and channel equalization.In this paper,the state machine and module interface of the module are designed according to the top-down design ideas.The look-up table is used to avoid timing constraints,and the use of multipliers is reduced by formula conversion.The above methods ensure the correct timing and minimize the loss and occupation of system resources.Finally,the paper verifies the designed RTL circuit.From the resource occupancy table,it can be seen that the resource consumption is relatively small,which meets the design expectations.There is a margin for the setup time and hold time on the entire module of channel estimation and equalization,which proves that the scheme is reasonable in timing and feasible.Furthermore,NI is used to verify that the design results of the RTL-designed module have good performance and meet the requirements of broadband micro-power system design.