Research And Design Of Channel Estimation And Equalization In NGB-W MIMO Mode

The previous communication network is usually divided into several nets, which work independently. With improvement of science and technology, the increments of system reliability will increases the bandwidth of system by the use of new technology, which causes great burden to the limited spectrum. At the same time, as the widely use of digital business integrates the networks such as telecommunications, broadcasting and television, it is necessary to merge these separated nets and share their resource in the next generation network.As a new generation of intelligent multimedia network the next-generation wireless broadcast network (NGB-W) has a new platform for the bidirectional transceiver, which can also carry the business of tri-nets to provide personalization services for users. The system based on the China Mobile Multimedia Broadcasting (CMMB) protocol and added new NGB-W mode can choose the different solutions for data transmission according to characteristics of different business. NGB-W model adopt MIMO-OFDM system to achieve the baseband processing unit. Because of the channel fading, it's important to study the channel estimation and equalization. This paper found a solution to the channel estimation and equalization unit implementation based on the NGB-W protocol.Firstly, the NGB-W baseband processing system and the key technology has been studied. In addit ion, the characteristics of wireless channel fading and MMO-channel model has been analyzed.Secondly, it discussed non blind channel estimation algorithm for MIMO-channel, which includes LS algorithm and MMSE algorithm for pilot estimations, the linear interpolation, time-domain interpolation, quadratic interpolation and wiener interpolation for channel interpolation, the MMSE algorithm and ZF algorithm for equalization. According to the result of these algorithms simulation at MATLAB, it gives the realization plan of channel estimation and equalization.Thirdly, this paper designs the hardware implementation method and Verilog coding for the realization plan. This implementation uses the parallel select register mode innovatively to save the resource in channel estimation.Finally, the Verilog code has been synthesized and the resource utilization has been analyzed, moreover the module has been run on FPGA.