Research On Flash ADC-based Digital Low Dropout Regulator

To provide stable dc voltage or dynamic voltage scaling in multi-core system-on-chip design,low dropout regulator is widely used as post-regulators following dc-dc converters.Compared with the analog LDO,the digital LDO provides lower voltage operation,better process scalability,and better stability,making it suitable for digital systems.In this thesis,recent digital LDO architectures are well studied,and a flash ADC-based digital LDO is proposed.A true flash ADC with non-linear decoding enables dynamic loop gain for enhanced transient response.The exponential-ratio array not only expands the load range of the digital LDO but also improves the searching efficiency of the control word.Designed in 65 nm CMOS,the proposed digital LDO achieves a load ranging from 17?A to 82.7mA,when the input and the output voltages are 1.0 and 0.9V,respectively.Compared with other works,the digital LDO achieves a settling time of 70 ns with a load step of 40 mA,exhibiting the shortest normalized settling time is the shortest.A new figure-of-merit is proposed for fair comparison with other state-of-the-art digital LDOs.The proposed digital LDO achieves the best performance with the new FOM.Based on the proposed flash digital LDO,a fully integrated two-stage digital LDO architecture for robust frequency generation under low supply voltage is proposed.The digital LDO designed for the VCO in the PLL provides constant or temperature-compensated supply voltage with a 1-bit ?? modulated fine loop,while offering fast transient performance over load current jump with the multi-comparator coarse loop.The proposed digital LDO designed in 65 nm CMOS generates a noise-shaped output whose peak value is less than 1mV with a 200 pF on-chip capacitor.A dropout voltage of 50 mV from a 1.0V supply is achieved with the load current ranging from 2.0?A to 13.0mA.The proposed digital LDO achieves a minimum resolution of 2?A with a peak current efficiency of 99.8%.Under the regulated supply from the proposed digital LDO,all the spurs at the PLL output are shown to be less than-40 dBc.