Research And Design Of CAN Bus Controller Based On FPGA

With the continuous improvement of living standards,consumers have put forward higher requirements for the versatility of automobiles,and the number of automotive electronic control devices such as car audio and video,GPS navigation is increasing.The wiring harness connection between these electronic devices is complicated and consumes more energy.Therefore,the centralized wiring inside the automobile and the interconnection mode of each electronic control devices need to be further improved to improve the stability and safety of the whole automotive system.The Controller Area Network(CAN)bus technology with the advantages of strong real-time performance,low cost and high reliability has emerged corresponding to the requirement.It has developed into the only field bus technology with international standards that is widely used in many fields such as automobile,medical instrument and industrial automation.Based on the CAN 2.OB bus protocol specification,the design of CAN bus controller is deeply studied in this thesis.The main contents of this thesis are as follows:Firstly,in this thesis,the overall function of the CAN bus controller is elaborated.In the design of the program structure,the "top-down" design method is adopted to divide the bus controller into three independent and associated modules of registers,bit timing logic and bit stream processor.According to the functional requirements of each module,the bit timing logic module can be divided into sub-module of bit timing,sampling points and bit synchronization design,and the bit stream processor module can be divided into bit stuffing,acceptance filter,CRC,FIFO,transmmiting and receiving data module design.For each module,Verilog HDL codes are written for functional description.Then,in this thesis,a simulation verification platform is built up.Test stimulus code program is performed with the simulation of ModelSim software to verify the function of registers module,bit timing logic module and bit stream processor module.By analyzing the simulation waveforms,it can be proved that each module passes the simulation under the condition that the clock cycle is 62.5ns,and all of them achieves the functional requirements of CAN 2.OB protocol specification.Finally,the RTL-level circuit is obtained by synthesizing the designed CAN bus controller,and the comprehensive report shows that the designed CAN bus controller has low resource consumption.All the designed modules perform board-level verification on the FPGA,focusing on the verification process of the CRC check module.The static timing analysis report shows that both the slack values in the setup time and hold time are positive,which indicates the timing requirements are met.The maximum clock frequency is 250MHz,which also meets the requirement of information transmission rate of the CAN bus.In the meantime,the board-level verification waveform displayed by SignalTap ? is consistent with the waveform plotted by ModelSim simulation,verifying the correctness of the design.