Design And Optimization Of Projectile-borne High Frequency Pulse Recorder

Whether fuze system work reliably and stably determines whether the weapon effectiveness can be fully realized.Therefore,it is very necessary to verify whether the signal quality of the fuze output meets the system design requirements in the application environment.According to the demand of an institute,a acquisition storage device(sampling speed ?500MHz,resolution not less than 8bit,input impedance ?1M?,input capacitance ?8pF,etc.)is designed which used to record the high-frequency pulse coded signal that a fuze outputs.According to the requirements of technical specifications and on the basis of inheriting previous studies,this paper optimizes and designs a high frequency pulse recorder with FPGA as the main control,SSRAM and Flash as storage medium with the sampling frequency up to 500 MHz.The recorder of previous studies have problems or deficiencies such as heat,insufficient ADC adaptation,and impedance mismatch.In view of the existing problems,based on the transmission line theory and signal-to-noise ratio,considering the influence of the transmission line effect and the distribution parameters of the resistor and capacitor in the circuit,the article focus on the circuit designing and optimizing in detail,such as frequency compensation divider circuit,front and rear terminations of the ADC circuit and the coupling capacitor of the digital power supply circuit.Taking noise and signal-to-noise ratio as consideration parameters,the noise and signal-to-noise ratio are analyzed in the process of design and optimization of impedance transformation,ADC front-end matching,sampling clock,analog power supply and other circuits.Based on the distribution parameters of transmission line,the simulation design of the PCB of the recorder is carried out.The PCB stack-up and impedance control are designed in detail by using the software Polar SI9000.Based on the constrained driving principle commonly used in high-speed PCB design,LVDS signal line and key single-end microstrip signal Integrity simulation analysis and PCB stack-up and layout are carried out with the help of EDA software Cadence.The simulation of logic function of recorder memory is carried out in the logic design part.The performance test results of the recorder indicate that the recorder has been optimized and improved.It have achieved the performance parameters such as 500 MHz sampling rate,12 bit resolution,1M?input impedance,5pF input capacitance,which meets the technical requirements.