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Design And Implementation Of Satellite Integrated Processing System Based On FPGA+DSP

Posted on:2018-07-22Degree:MasterType:Thesis
Country:ChinaCandidate:J LiFull Text:PDF
GTID:2382330569985382Subject:Control Engineering
Abstract/Summary:PDF Full Text Request
With the application of real-time image processing technology becoming more and more widespread in the territory of aviation and national defence,the amount of satellite image data processing is increasing,and the real-time requirement of the image processing system is becoming higher.This paper designs a real-time image processing hardware system with superior performance.Using the system,we achieve the hardware acceleration of the MCPM algorithm.This paper mainly introduces the design and implementation of the satellite integrated processing system based on "FPGA + DSP".The FPGA is used for image data acquisition and image processing.The DSP is used to implement high-level complex image processing algorithms.This paper first introduces the overall design of the satellite integrated processing system.According to the needs of the system analysis,we design the system and main device selection.Then we introduce the hardware circuit design of each module of the system,describe the realization mode,design basis of each module in detail,and ensure the safe,stable and reliable work of the system.At the same time,we introduce the various interfaces in the system and complete the FPGA implementation of each interface.The FPGA implementation process of EMIF interface is introduced in detail.A MPCM algorithm for infrared weak target detection is introduced in this paper.Although the algorithm is simple in structure,it is still difficult to achieve real-time requirements when using CPU only.This paper designs FPGA to realize the hardware acceleration of MPCM algorithm,and can meet the real-time requirement of the system.The paper points out the shortcomings of the system and the direction of further research.This design of the satellite integrated processing system has been completed all the tasks and indicators of the requirements.All the pathways of the integrated processing system are tested successfully.The system completes sending received image to the display shows,and to achieve MPCM algorithm FPGA hardware acceleration.The system detects a resolution of 512 × 512 infrared images using only 1.72 ms,and meets the system real-time requirements.
Keywords/Search Tags:Field Programmable Gate Array, Digital Signal Processor, Integrated Processing System, Hardware Design, Target Detection, Hardware Acceleration
PDF Full Text Request
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