BCD Process Optimization And Reliability Verification During Fab Transfer

Fab transfer is common in the semiconductor industry.No matter for IDM or Fabless,in the drive to reduce manufacturing costs,expand capacity,meet supplier diversity requirements and other factors,fab transfer will inevitably become an urgent need during enterprises development.Owing to the particularity of BCD process,even under the same process standards,the fab differences at machines,basic process parameters and materials suppliers will cause inconsistent product quality.Therefore,specialized process optimization and reliability verification are necessary for fab transfer.In this paper,the BCD process optimization and reliability verification are taken as the research object,related process problems and reliability verification methods during fab transfer are discussed in detail.The main contents are:1.Optimization on VIN pin breakdown voltage.The root cause of the low breakdown voltage problem is found as the punch-though between VIN of N-well and the VOUT of N-well.The voltage of punch-though is lower than BV_ds of PMOS where VIN locates,and cause VIN breakdown voltage to drop down.Next,after improving the performance of adjacent P_well STI,distance of adjacent N_well,buried layer annealing time and Epi recipe,self-doping effect during the Epi growing up is discovered as the major reason that leads to N wells punch though.In addition,the optimized one-step temperature ramping up Epi growth method can obviously inhibit the negative effect of self-doping,thus effectively increase the breakdown voltage of VIN pin.2.Optimization on poly fuse.For the bad trim issue during fab transfer,based on the analysis of poly fuse structure and its modification method,the bad trim issue is found to be closely related to ILD layer materials through experimental analysis.The optimized SION material significantly improves the success rate of trimming,which is a better solution to fix above problem.3.Reliability verification.For the need of reliability verification during fab transfer,the scheme is mainly considered from two sides:one is from chip-level,the other is from system-level.The chip-level reliability verification scheme is mainly based on the JEDEC standard,and the purpose is to evaluate the risks that happen at fab and assembly side.The system-level reliability verification is based on the product application,by means of collectting data through the Burn-In test,analyzing the product early failure rate,and estimating product life time and LTDP,to provide assurance for smooth mass production.