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Research And Design Of Wide-band Controllable Frequency Source

Posted on:2019-06-28Degree:MasterType:Thesis
Country:ChinaCandidate:F YuFull Text:PDF
GTID:2348330569987750Subject:Electromagnetic field and microwave technology
Abstract/Summary:
Frequency source,which is the important component of communication system,influences the performance of communication system and hence gets the great attention,Low phase noise,high frequency,wide bandwidth,high output power,low spur levels,fast frequency conversion,and small frequency step are the goals in frequency source design.According to the design requirements(frequency output is 8-10 G,output power is more than 10 dBm,output frequency resolution is less than 100 Hz,phase n oise is lower than-75dBc/Hz@1k Hz,-80dBc/Hz@10k Hz,and-90dBc/Hz@100k Hz under the 50 MHz reference frequency,and stray is better than-42dBc),a proper design scheme is determined,in which DDS is utilized to drive PLL.The accomplishment of design requirements relies on hardware design,including the design of FPGA,DDS,PLL,filtering and amplification,and the software design,including the compiling of control program by Verilog HDL in Quartus II.This thesis is organized as follows.In section Ⅰ,background,significance and actuality of frequency source are presented,and the main works and chapters are also introduced.In section Ⅱ,the basic theories of frequency source are presented,the compositions and principle of DDS and PLL are introduced and the advantages and disadvantages of DDS and PLL are analyzed,at the same time,spur levels and phase noise are analyzed,setting the foundation for the later design.In section Ⅲ,several hybrid frequency synthesis techniques are introduced and the advantages and disadvantages of them are analyzed.In addition,the feasibility of selected architecture,chip,phase noise and stray are analyzed to determine the final project.In section Ⅳ,the designs of hardware and software are introduced in details,the problems of the designs of FPGA module,DDS module,PLL module,filtering and amplification module,and test are researched and solved.Besides,the Verilog HDL program is explained.The time sequences of DDS and PLL are analyzed.The filters,including capacitive inductance filter and parallel coupled line filter,are designed.In section Ⅴ,the pictures of real products and the test results are shown,such as power,phase noise and stray,indicating that the design requirements can be satisfied well by the selected scheme.In section Ⅵ,the conclusion is given,the main work of this paper and the advantages and disadvantages of the design are described.
Keywords/Search Tags:FPGA, DDS, PLL, filtering and amplification
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