Research On Key Technology Of Fully Integrated LDO Based On Advanced Technology

Ultra-low-power fully-integrated voltage regulators with fast load-transient performance are highly attractive for low-power systems-on-a-chip?So Cs?.In such systems,the digital units working in the subthreshold region are more sensitive to supply variations.The digital low-dropout regulator?DLDO?is more suitable for low-supply-voltage operation,as compared to an analog LDO regulator.But,traditional DLDOs are either slow or power hungry,and need a large output capacitor?consumes area?to survive a fast load transient.When a higher clock frequency is used for faster response,both the current efficiency and the loop stability are degraded^[1].An analog-assisted?AA?loop was used to provide a high-pass loop in parallel with the slow digital loop for fast response.However,a large coupling capacitor?100pF?was still needed,trading off area with power and speed.An NMOS power stage as a source follower is sometimes used in replica LDOs and cascaded LDOs for its intrinsic response to load transient;the NMOS source follower naturally provides more output current when VOUT drops.To improve upon the power-speed-area tradeoffs,this paper presents a DLDO using NMOS power switches,and employs a NAND-gate-based highpass analog path?NAP?to assist the slow low-power digital loop.With these two techniques,nearly two orders of better Fo M is achieved relative to the state-of-the-art.An ultra-low power reference voltage generator?RVG?is implemented in a commercial 40-nm CMOS technology.The circuit consist of a nanowatt bandgap reference?BGR?which temperature coefficients is only 12.9 ppm/?,and a low-dropout regulator?LDO?.The proposed circuit benefit from the duty-cycled working technology and have only 60nW power consumption.The LDO makes use of the FVF structure to achieve high low-frequency loop gain and robust stability.