A Column-Level ADC Design For Readout Circuit

ADCs for read-out circuit of the image sensor are divided into three categories: pixel-level ADC,chip-level ADC and column-level ADC.The column-level ADC converts one column of pixel signals row-by-row,which does not increase the area and power consumption of each pixel compared with the pixel-level ADC,and the pixel fill factor is large.Compared with the chip-level ADC,the conversion rate of the column-level ADC is low.Moreover,the column-level ADC is applicable for reading large pixel arrays due to its multi-channel parallel operation,but it has the fixed pattern noise.The goal of this project is to design a 12-bit,4.8KHz column-level ADC,and the single-slope ADC can precisely meet this low-speed and high-precision requirements.Moreover,the simple column-level circuit structure of the single-slope ADC makes it easier to ensure consistency between the columns,thus minimizing the fixed pattern noise.In addition,counter and ramp generator in the single-slope ADC can be shared by each column,which is superior to other column-level ADCs in area and power consumption.This article mainly introduces the entire design process of the single-slope ADC,including the structure determination,core module design and simulation,layout design,and overall simulation.Among them,the working principle and design method of the core module are elaborated in detail.The core module includes a ramp generator,an output buffer,a comparator and the sequential circuit.The slope generator uses the segmented capacitor DAC structure to reduce the chip area.In this paper,the working principle,non-ideal factors and design points of the segmented capacitor DAC are introduced in detail.The output buffer is implemented by a high-gain op amp with unity-gain negative feedback structure.The structure selection and design method of the high-gain op amp are analyzed in detail in this paper.The comparator in this single-slope ADC has rail-to-rail input range and offset voltage calibration function,which significantly increases the input range of the single-slope ADC and reduces the fixed pattern noise.The principle of the rail-to-rail input and offset calibration of the comparator is described in detail.Finally,the design method of the comparator is introduced.The timing design of this single-slope ADC uses the transmission delay of asynchronous counter and D flip-flop to ensure the stability of key signals.In this project,author designs a 12-bit single-slope ADC based on 0.18μm CMOS process and 1.8V supply voltage.When the input is 2.33 KHz full swing sine signal and the sampling frequency is 4.88 KHz,the effective number of bits in the TT process corner is 11.51 bits.The signal to noise and distortion ratio is 71.08 dB.The total harmonic distortion is-77.17 dB and the power consumption per column is 157μW.