The Design And Implementation Of AES Algorithm Based On FPGA

Twenty-first Century,is the era of rapid development of the Internet.The network brings convenience to people,but also brings unprecedented security threats at the same time.Encryption technology is an effective method of protecting information security.The Advanced Encryption Standard(AES)encryption algorithm has been widely used in many fields since its publication,and has played a key role in protecting information security of people.This paper mainly designs an hardware structure of AES encryption and decryption algorithm based on FPGA,which supports three different key lengths of 128/192/256 bit.The structure employs non-feedback mode and hybrid pipelining,making full use of parallel computing advantage of FPGA and improving throughput of AES encryption and decryption algorithm.This paper is optimized in terms of throughput and area on the basis of ensuring correctness of AES algorithm.The main work is as follows:(1)The pre-computation technology is used to solve the problem of low throughput of AES algorithm using composite field combinational logic.This paper eliminates and mergers some calculation processes of multiplicative inverse to reduce the length of critical path,then divides into new pipelining stages.The number of logic gates on the critical path is reduced 32% at the expense of some extra XOR gates and 4-bit multiplexors after the multiplicative inverse is optimized.(2)The method of sharing resource is used to reduce area.In this paper,it employs multiplexing multiplicative inverse in the the InvSubBytes and SubBytes to reduce area,at the same time,the matrix constant in the invmixcolumns/mixcolumns is decomposed into two constant matrices so that the invmixcolumns can be multiplexed with the mixcolumns to reduce the area,one of which is a constant matrix in the MixColumns,the other is a new constant matrix.(3)This paper designs the hardware structure of AES encryption and decryption algorithm,which is implemented based on Verilog HDL language,and the function simulation is carried out in Modelsim 10.4 environment.The design is synthesized with different types of FPGA to obtain the required parameters of performance by Xilinx ISE14.7,and compared with previous research results.The result of function simulation shows that the AES encryption and decryption hardware structure can correctly encrypt and decrypt.The synthesized report indicates that the maximum frequency is 756.23 Mhz on Kintex-7 xc7k410 T tfbg676-2 of FPGA,the throughput is 96.80 Gbps,and throughput/area is 4.54 Mbps/slice,which satisfies expected requirements of research group.