Design And Implementation Of Video Acquisition And Edge Detection Systembased On FPGA

In the information age,Obtaining information and processing information through electronic systems is the mainstream of life and production.A surveillance system integrating video capture and image processing occupies a very important position in traffic,safety,environment,industry,medical and aerospace fields.Video monitoring technology has developed from the analog signal transmission to the stage of digital signal processing.Function is no longer a simple image transmission.In order to adapt to the rapid development of society,we will put more complex functions on it,for example,target detection,target recognition,face recognition and so on.To achieve these functions,the first step of image processing is always edge detection.On the basis of obtaining the edge of objects,more complex functions are implemented.Therefore,it is of great significance to study the real-time edge detection system.It should not only be highly realtime,that is,at the same time of achieving functions and can not affect the fluency of the whole video surveillance system,but also has a good accuracy,that is,a reasonable algorithm for edge detection.Compared with the implementation of software,the hardware implementation has a higher speed,can handle a larger amount of data,and can be flexible to transplant the system.In this paper,several mainstream edge detection operators are simulated on the MATLAB,contrasts and screens were did among them as well.Finally,the Sobel operator was selected to implement the edge detection on the hardware platform.Because of its parallel operation characteristic,FPGA has great advantages in high-speed data processing.The system selects it as the main control chip,it released commands to the entire system and performed data exchange and processing.Peripheral hardware were controlled by using the control module formed within the FPGA.Under the coordinated control of FPGA,a video acquisition and edge detection system was composed of camera,memory chip and display.The whole system consisted of a camera as the beginning data flows,after a camera,a SDRAM caching chip,and an algorithm model,finally,the VGA driver module driven the indicator to output the image of the 640*480 resolution.All functional modules had been simulated before the experiment.Pipeline design,as the key technology in this system,effectively improves the efficiency of the system.In this paper,the idea and process of pipelining design in the Sobel algorithm module were expressed through the analysis of TP diagram.At the same time,the improvement of the Sobel algorithm itself was also explained.Finally,after connecting each of the hardware modules to the FPGA chip,the project was compiled and constrained in Quartus II,and downloaded the project to FPGA chip under the JTAG interface,by observing the result of the edge detection through the indicator,the realization of the system function was proved.