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Design Of Digital Transceiver Based On Multichannel Signal Synthesis And New Filter Combination

Posted on:2019-06-21Degree:MasterType:Thesis
Country:ChinaCandidate:G S LiFull Text:PDF
GTID:2348330545461567Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
With the rapid development of science and technology,mankind has made remarkable achievements in radar detection.The improvement of chip performance and manufacturing technology further makes the digital transceiver get more extensive and in-depth application,and develops rapidly towards high-performance,multi-purpose,small volume and low power consumption,and its function is improving day by day,in the range of radar communication and detection,the role played by the digital transceiver is becoming more and more important.The advantages of DDS(Direct Digital Synthesizer)technology,such as low cost,low power consumption,high precision and fast conversion,as well as high speed processing,easy to realize and run smoothly of Field Programmable Gate Array(FPGA)are more obvious,they provide a reliable and stable hardware platform for the realization of various frontier electronic technologies.Based on the above arguments,the thesis begins with the design of digital transceiver based on multichannel signal synthesis and new filter combination.First of all,the thesis conducts a detailed study on the relevant theories of digital transceiver.The theory mainly includes signal generation,analog-digital conversion of signal,digital mixing and decimation.Secondly,the thesis of paper is designed and the main components are selected according to the specific performance index of the radar.A type of meteorological radar requires a detection distance of at least 6km and a maximum of 75km and a dynamic response of 85dB.In addition to having good detection performance,it should also take into account the modularity and low power consumption.According to the performance requirements of the radar,in order to achieve effective blind processing and efficient signal recognition and solve the problem of low resolution and anti-jamming performance due to the single channel transmission of multichannel signals in a traditional digital transceiver,the thesis designs digital transceiver to generate three independent signals of different durations and frequencies,which are respectively filtered and synthesized and sent to analog upconversion,the digital down-conversion part of digital transceiver to meet the dynamic requirements of 85dB,the design of the paper uses sampling chip of 16-bit accuracy to convert the received analog signal to digital signal.In order to achieve low power consumption and reduce the occupation of system resources,the decimation and deceleration module of the digital down conversion part selects a new filter combination,It cascades the CIC filter with the Invsinc filter and extracts the high-speed signal,and finally obtains the phase quadrature signal of IQ.Thirdly,the feasibility of the thesis design and FPGA code are verified to verify whether the thesis design can achieve the overall function of the digital transceiver,successfully generate the signals needed by the radar system,successfully digital down-convert the radar echo and restore the signal,and whether the thesis design can meet the dynamic performance requirements of the radar.The simulation tools used in this thesis are MATLAB 2012b,Quartus ? 13.0 and Modelsim-Altera.At the end of the thesis,through the circuit design of the used chips,the printed boards are delivered to produce the hardware physical products.Power the module and use the spectrum analyzer to see if the digital transceiver successfully generated the signal and successfully restored the received signal.Through rigorous theoretical study,code design and testing,it is concluded that the thesis design is in full compliance with expectations,that it can be delivered and used in practical engineering,and that it can be used for reference by other related designs.
Keywords/Search Tags:Digital Transceiver, DDS, CORDIC, CIC, FPGA
PDF Full Text Request
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