Implementation Of HEVC Motion Estimation On BWDSP Platform And Optimization Of Memory Access

In recent years,with the HD resolution(HD)and ultra-high resolution(UHD)applications gradually into the people's vision,video compression technology has been a huge challenge.In addition,the problems of high-bandwidth video transmission and larger-capacity storage required by these HD and UHD videos have remained major research subjects in recent years.To address these problems,the Joint Collaborative Team on Video Coding(JCT-VC)developed the high efficiency video coding(HEVC)standard in January 2013,which is a successor to H.264/AVC(Advanced Video Coding).The goal of HEVC is to achieve about a 50%bit-rate reduction over high profile H.264/AVC given the same objective video qualities.Inter-frame prediction is a key technology in video compression coding.It mainly includes two parts:motion estimation and motion compensation.The motion estimation algorithm is a key technique in the video coding inter prediction algorithm,which has a very important influence on the video coding performance.In the latest video coding standard H.265/HEVC,it is proposed to use sub-pixel motion estimation using DCT interpolation filter(DCTIF),but the computational complexity is large,especially for high-resolution and ultra-high resolution video coding applications The BWDSP is developed by China Electronics Technology Group Corporation 38th Research Institute,can be widely used in a variety of high-performance computing areas,such as radar,electronic warfare,precision guidance,communication security,image processing and other signal processing.In this paper,the sub-pixel motion estimation of HEVC is realized and optimized on the BWDSP platform.The main work and innovation of the paper are as follows:1.The motion estimation consists of two parts:the integer pixel motion estimation and the sub-pixel motion estimation.The algorithm complexity and computation are very large.In this paper,we combine the BWDSP architecture with the BWDSP instruction set to calculate the SAD,SATD and sub-pixel in the high density data during the motion,estimation process.After optimization,the HEVC motion estimation on the BWDSP platform is significantly reduced compared to the number of clock cycles before optimization.Improved encoder performance.2.HEVC coding requires a large data throughput,due to BWDSP chip limited on-chip memory space,reference frame images may be stored in off-chip memory,BWDSP chip access to off-chip memory is very slow,and so in the process to With DMA to a large number of off-chip data first transmitted to the chip,and then access it.In this paper,the cycle Buffer is used to optimize the data access of the memory access.The cycle Buffer usually has a read pointer and a write pointer.The read pointer points to the readable data in the ring Buffer,and the write pointer points to the writable Buffer in the cycle Buffer.Data read and write of the Buffer can be achieved by moving the read pointer and the write pointer.Through the optimization of the access to the reservoir,the efficiency of the data reading process has been greatly improved.