Design And Verification Of SPI IP Core Based On APB Bus

With the development of integrated circuit technology,IP core reusable technology and FPGA-based verification technology in the chip research and development process occupies an important position,by more and more attention.Tracking the development trend of technology,combined with the requirements of ZX211411 project,this paper designs an SPI IP soft core based on APB bus,and carries out simulation verification work.Depth study of APB bus and SPI protocol features,the needs of the analysis,on the basis of the completion of the overall structure of the SPI IP core design,the division of the functional modules.The APB interface module,the register module,the baud rate module,the sending module,the receiving module and the interrupt module are designed in detail using the Verilog language.The IP core can also support the APB and the SPI protocol,and supports multiple data formats.Timing transmission mode and host / slave operation mode.The APB interface module encapsulates the bridge circuit in the IP core,so that the CPU can directly operate the IP core data,and can write all the data at once,improve the CPU efficiency;baud rate module using two-stage frequency Algorithm,can support most of the international standard baud rate,saving hardware circuit resources,user-friendly configuration baud rate information;data transceiver module using edge detection method to extract the trigger signal,compared with other designs,reducing the state machine redundancy State,improve the efficiency of data transmission.The verification platform is divided into three parts,namely APB read and write task module,validated SPI IP core and incentive response module.According to the test scheme and test case,the incentive platform is loaded in the verification platform to obtain the response,To confirm whether the response meets the expected functional objectives until all the functional points of the IP core are implemented correctly.Based on FPGA-based hardware simulation,the resource consumption report,timing report and power consumption report of IP core in practical application environment are obtained,which verifies the feasibility and correctness of SPI IP core performance,resource cost and power consumption.The simulation results show that the maximum operating frequency of the IP core is 200 MHz and the resource occupancy rate is less than 15%.The simulation results show that the IP core has reached 100%.SPI IP core overall performance is good,to meet the design requirements.