Research On The High Dynamic Range Imaging And Display Technology Based On SoC

With the progress of technology,the scenes of the nature world will be shown in computer more realistically.HDR imaging technology revolutionizes the field of computer graphics and other areas,such as virtual reality,security monitor,industrial engineering testing,and machine vision,etc.Nowadays,high dynamic scene acquisition function is becoming increasingly common in CMOS and CCD image sensors.And processing technology using these sensors is attracting more and more attention.High dynamic video has higher data processing capacity than normal video,which results in a higher processing bandwidth for the system.Compared with the traditional processing tools(DSP,CPU),FPGA has the higher parallel processing speed and flexibility depending on the smaller granular gate array structure,so using the basic logic gate design hardware circuit can complete the image algorithm and achieve high acceleration processing for dynamic scene data.However,FPGA has some features including weak system control,poor portability of functional modules and long development time of the project.So C-FPGA chip flexibly applies the pipeline parallelism processing of FPGA system and systematic control ARM,so it is a suitable solution platform for high dynamic video processing system with the large amounts of data.Based on So C high dynamic range imaging and display technology,this article includes hardware and embedded software design.The hardware section includes image sensor board-level PCB design and drive debugging,as well as video data reception and display.To begin with,completed the high dynamic image sensor drive and readout circuit design,and configure the registers of the sensor to achieve the normal high dynamic image acquisition in real time.Secondly,the tone mapping algorithm is validated in Matlab environment.And the effect of bilateral filtering and guided filter in the filtering process of TMO is compared.Meanwhile,compare the influences of different compression and extension curves on the image high dynamic compression.Then,utilizing the Verilog HDL,fulfill the TMO module of guided filter,color space conversion module,the logarithmic transformation module and gamma correction module of the image brightness non-linear adjustment.Furthermore,the IP core package of the above modules based on the Avalon bus interface is achieved.Finally,use the Qsys tool to instantiate video processing IP components and hardware system consists of ARM hardcore.Through the C program,embedded software designing completes the image sensor drive configuration as well as register information in read and write IP core,etc.In the system validation procedure of the article,check the proposed hardware architecture and the algorithm performance.Load the system configuration file generated and compiled by the Qsys tool into the FPGA,and at last,run the compiled program on the hardware system to complete the entire video system verification.After observing the experiment data,the hardware architecture designed in this paper can deal with the scene video information collected by the high dynamic camera in real time,at the same time,the more rich details of the scene can be shown on the LDR display.