The Design Of Time-frequency Synchronization Module In Wireless Lan Based On FPGA

As communications technology continues to innovation and development,and more and more mobile communication devices have produced and used,People's eyes begin to gradually shift the wireless network access from the wired network access,began to focus more in line with the needs of people living,more flexible and convenient wireless local area network.The development of wireless local area network,not only to bring great convenience for people's lives,but also to promote the continuous progress of human communication technology.In the wireless local area network design,how to make our information quick and accurate is one of the key people have been studied.As a typical modern semi-custom circuit of field programmable gate array(FPGA),its flexibility is more advantageous than the full custom circuit,the scale is bigger,with the ever-increasing storage capacity and soft-core implants,the scope of FPGA applications will be increasing.Thus,the research and design of FPGA applications in wireless LAN will be widespread concerned.The main contents are studied for wireless LAN physical layer time frequency synchronization technology and FPGA implementation method.It introduces the characteristics of the wireless local area network data transmission and the principle of time frequency synchronization techniques,combined with FPGA hardware characteristics,it describes the design and implementation in detail of down-sampling module,CORDIC module,coarse/fine frequency offset estimation module and the FFT module in time frequency synchronization based on FPGA.And design the chromatic dispersion estimation module.For each module,specifically addressed the implementation of the algorithm design and implementation on FPGA,and completed the FPGA design of each module.Finally,using MATLAB simulate the algorithm of each module and for the FPGA implement of each module,simulate and verify in the Quartus II software.The results demonstrate the feasibility and correctness of the algorithm design and FPGA implementation,achieved the desired purpose.Analyzed and summarized the shortcomings and deficiencies on the design,and proposed improvement measures.