Structure Reinforcement Technology Of NoC MBU Soft Errors Tolerance Based On Two-Dimensional Error Coding

Because of the higher integration of circuit and needs of application,SoC has gradually transferred from bus-based single-core or many-core architecture to NoC-based multi-core architecture.At the same time,as the technology of Integrated Circuit(IC)developing fast,the smaller feature size and lower voltage make the soft errors occuring frequently in deep sub-micron ICs.On the other hand,influenced by the increased number of transistors per unit area and narrowed the distance between devices,high energy particle bombardment may cause multiple charge and discharge of the adjacent nodes simultaneously,and caused Multiple Bit Updates in sequential logic unit.Since errors are more likely to happen as the integration of circuit become higher,how to correct MBU soft errors in multi-core Noc is a problem that needed to be solved urgently.In order to solve these problems,this paper has proposed the Two-Dimensional error coding which can detect and correct errors in the NoC virtual channel memory,consequently the multi-cores NoC structure can be reinforced.The summary of the project is listed below:1)According to the fast increased number of MBU soft-errors of NoC in deep sub-micron ICs,this paper has used the Two-Dimensional error coding in the virtual-channel of NoC.It has many advantages,such as high error correction,easy to implement and small area.We have proved that in the same condition the extra area the NoC MBU Soft Errors Tolerance Based on Two-Dimensional Error Coding needed is much smaller than conventional ECC coding.2)This text uses high-level language(C++)modeling to realize two-dimensional error correcting codes,and has verified the correctness of this code using in the NoC to tolerant MBU soft errors.By comparing the performance of NoC MBU Soft Errors Tolerance Based on Two-Dimensional Error Coding to conventional ECC coding in the same condition,we proved that two-dimensional error correcting codes has a much higher correcting rate than conventional ECC coding.3)This paper has used the hardware description language(Verilog)to realize the simulation on virtual channel in worm hole structure router,and assessed the hardware cost.It has also made the hardware cost comparison between Two-Dimensional error coding and conventional ECC coding,which shows that the area and time costs of NoC MBU Soft Errors Tolerance Based on Two-Dimensional Error Coding is far less than conventional ECC coding.