Design Of Hardware-software Co-design Of Voice Trigger Chip With Low-latency Solution

With the develop of information technology,non-contact human-computer interaction is attracting people's attention with its convenient and speed.Natural language,as the main way of communication between human beings,has gradually become one of the main non-contact human-computer interaction.People hope to operate the computer through a simple voice command.With the progress of technology and innovation,voice interactive technology has been widely used in the computer system.With the rise of mobile Internet,voice interactive technology has gradually been applied in the mobile terminal.Mobile terminals tend to use battery-powered,and a long time in the recognition state will consume a lot of energy,therefore the mobile terminal system is used to active the voice recognition system by bottom or screen.In view of the above situation,people propose to design a low-power voice trigger chip which can identify for a long time to solve the problem.Low power consumption limits the computing power of voice-triggered chips,and how to provide fast and accurate recognition results with limited computing power becomes a challenge.In this paper,the MFCC feature extraction process,the GMM-HMM speech recognition algorithm and the VAD detection algorithm are studied.Based on the results of the analysis,a set of low latency optimization solution is proposed in detail analysis of the operation time and main operation of each step.The low latency optimization solution includes hardware optimization and software optimization.In hardware,the use of SRAM as a program space to speed up the speed of CPU instruction fetch;design hardware and multiply-add operation and single-Gaussian likelihood calculation unit to accelerate the main time-consuming calculations.The latency of the system identification is reduced by using the method of space-time,using the look-up table,the polynomial fitting and the probability calculation of the same HMM state.Based on the optimization solution,this paper designs a voice trigger SOC chip with AndesCore N10 as the core,and tests the voice trigger system based on the chip.The SOC chip using TSMC 0.13 um technology production,the core for the AndesCore N10.Peripherals include high-precision Sigma-Delta ADC,GPIO,SPI and other modules.The average latency of our voice trigger system base on the chip was 9.952 ms,recognition rate and false recognition rate were 95.5% and 0.5%.In the office environment,the number of false triggering system is less than 1/day.The result of the research has a good reference value for further application of voice trigger chip in mobile terminal.