Research And Hardware Implementation Of Particle Filter Based On FPGA

Particle filter is a filter algorithm of Bayesian estimation theory and Monte Carlo method, the basic idea is to use a set of random samples in the state space, to approximate the posterior probability density function based on Monte Carlo method for estimation of state. For nonlinear,non-Gaussian system has a high degree of adaptability, and the accuracy of its approximate optimal estimation, has become one of the most popular filtering algorithms.Firstly, particle filter algorithm research status and background and significance are introduced, and then start from the Bayesian estimation and Monte Carlo method, the sequential importance sampling algorithm is analyzed in detail, and the particle degradation problem of the importance of function and re-sampling are introduced, then introduces the basic particle filter algorithm. Because the particle filter algorithm needs a large number of particles to participate in the operation, the particle filter has the disadvantages of high computational complexity and poor real-time performance. In this paper, the particle filter algorithm based on resampling is improved and simplified. This paper introduces the common polynomial resampling, system resampling and residual resampling, and analyzes the complexity and operation speed of the hardware implementation. In order to further improve the real-time performance of particle filter algorithm,is improved based on partial resampling, proposed a resampling algorithm based on linear combintion, the resampling algorithm circuit structure is relatively simple, do not need to be normalized weight operation or simply copy the particle, but through the production of new particles linear combination, effectively avoids the loss of particle diversity. this algorithm can ensure the filtering precision, and greatly reduce the running time.At last, this paper gives a clear steps of the improved simplified particle filter algorithm based on two dimensional bearings only target tracking system. The hardware structure is mainly divided into sampling module, weight calculation module, sampling module and state estimation output module, and analyzes the parallel particle filter operation way, through which can be decomposed into multiple parallel PE units, decomposition of the particle processing tasks, so as to improve the real-time algorithm. Each module is described by the Verilog hardware circuit, and the function is simulated by ModelSim, which verifies the correctness of the hardware circuit. Finally, each module is connected to the FPGA development board to complete the design verification.