The Algorithm And Hardware Implementation Of The Probability Hypothesis Density Particle Filter

This paper has conducted research on multi-target tracking problem using Probability Hypothesis Density (PHD) particle filter algorithm and the hardware implementation of Probability Hypothesis Density particle filter algorithm.First, the algorithm on multiple maneuvering targets tracking problem is investigated. Due to its excellent tracking performance on maneuvering targets, the current statistical model is used to propose a new algorithm, named Current Statistical Model Probability Hypothesis Density Filter (CSM-PHD). Compared with multiple-model PHD (MM-PHD) particle filter algorithm, the proposed algorithm does not need any knowledge on the target motion model and avoids designing the model sets. Furthermore, the proposed algorithm does not have mode competition as this would happen in multiple-model PHD filter algorithm. Simulation results shows that the proposed algorithm has similar tracking performances compared with MM-PHD particle filter, but own faster processing rate and lower computational complexity.It is difficult to implement the standard PHD particle filter algorithm on hardware circuit because of the complexity of the algorithm itself. In this paper a simplified PHD particle filter algorithm is proposed, which uses the information of the estimated states at time k-n to select measurements at time k and this leads to fixed number of measurements to be processed by fixed number of circuit units at each time instance. Thus the algorithm removes the barrier of the number uncertainty of measurements in multi-target tracking problem. The proposed algorithm also takes the number of particles into consideration under the criterion of tracking performance, hardware implementation delay and computing complexity. Simulation results show that the tracking performance of the proposed PHD particle filter is similar to that of the standard PHD particle filter but is easier to be implemented using FPGA based hardware circuit.According to the simplified PHD particle filter algorithm, the paper proposed its hardware architecture, discussed each module of the circuit in detail and analyzed its time delay. The results of the hardware circuit from ISE chipscope is given and compared with the results from software, which verifies that the tracking performance of the proposed hardware architecture is similar to the results simulated in software. The analysis on the execution time shows the hardware of the algorithm has fast process ability. When at most three targets appear, the data process rate can reach up to 6kHz using a 50MHz system clock.