The Research Based On ATPG Of FPGA Netlist On Equivalence Verification Method

In recent years,the rapid development of science and technology,especially the application technology about the materials of nanotechnology and transistor continues to progress,so that people can integrate billions of transistors in the thumb size on the circuit,and it can meet people all aspects of demand.But with the design accuracy continues to increase,it lead to the increased complexity of IC design,and the complexity has become an exponential growth trend,so the errors in the design progress has more and more like come.When validating the integrated circuit,we can turn the integrated circuit verification pronlem into the SAT problem.When solving the SAT problem,we can use the Complete or non-complete algorithm.When using the complete algorithm to solve the SAT problem,It is based on the design of the integrated circuit and get the CNF which is equivalent in function to the testing integrated circuit.then we can solve the CNF to get solutions to verify the functional integrity of the integrated circuit.The advantage of the complete algorithm is however the regardless of the size of the conjunctive paradigm,we can find a set of assignments which satisfy the conjunctive paradigm and judge the the SAT problem is satisfied problem which is that the functions of the integrated circuit design is correct.In the case of no answers to solve the SAT problem,it can also prove the SAT problem is not satisfied such as the complete algorithm DPLL.However,it will aimless search and waste a lot of time when solving the SAT problem.The incomplete algorithm mainly concertrate on local search algorithm such as the D algorithm and ATPG algorithm.Although it can not guarantee the solutions for the tested problems,it is quick to solve the problem and especially for the special SAT problem.And it is more effective than the complete algorithm.For the shortcomings of traditional ATPG algorithm,we will introduce the LUT technology to alter the ATPG algorithm,and propose an improved ATPG algorithm which based on LUT technology.The main idea of this improved ATPG algorithm is we encapsulate the basic logic gate in a very large size which designers think no errors come out about VLSI,so that can reduce the number of failures during the test process and accelerating the entire test generation process.Based on the improved ATPG algorithm,we propose an equivalence verification method which based on the improved ATPG algorithm for FPGA netlist.At the same time,the recursive learning algorithm is added to the verfication method.During the test validation process,we will use the recursive algorithm to store the logical result for each node in the netlist,so as to facilitate the input and output judgments of the basic logic gates in the circuit and derive the logical constraint between them,for the better test of the circuit verification.The verification method not only tests and verificates the LUT module which contains a large-scale combination of circuit,but also supports the verification of FPGA which use various netlist such as EDIF.Therefore,it will greatly facilitates verification of the work of VLSI validation.