Design And Application Of Fault-injection Tool At RTL Level

As the development of Moore Laws.The process of IC has come to nanometers.The decrease of feature sizes makes the supply voltage lower and lower and frequency higher and higher.The Circuits becomes sensitive to EMI,crosstalk and particle strikes.The harsh environment such as Space,Medical Radiations and Automobile safety is now more and more care about the reliability of ICs.On the other side,because the scale of ICs becomes larger and larger,the test and estimation time cost is up quickly.The quick estimation of large scale ICs has become a research hotspot.This thesis designs and implements a fault injection tools at RTL levels based on the RTL level fault injection concepts.The Verilog-Perl is used to design lexical parser.By using it,the tools supports almost all lexical rule from Verilog1995 to Verilog 2005.The method based on checkpoint and parallelism makes the speed of fault injection increase several times than before.On the other side,this thesis researched how to get system cross section at RTL levels,and has gotten a method to get the system cross sectioni at RTL levels.And then,in order to verify the availibity of this tools in large scale ICs,a Open Risc microprocessor is radiation hardened.This thesis has built the software and hardware environment of Open Risc1200,and anaylzed the sensitivity of microporcessor.For the different sensivity regions,either the error detection D flipflops or the TMR method is used and the error detection handle circuits has been designed.Finally.This thesis judged the harden effect of hardened Open Risc1200 microprocessor.It compared the performance cost and radiation ability with before.28.1% extra area and 21.0% more power consumption leads the radiation ability increase 10 times according to the judgement.Also the dynmmic cross section of processor has been gotten.The saturation cross section is 2.5e-6c?/device after harden design.