Bit Reliability Based Joint Detection-Decoding Algorithms And Decoder Design For Nonbinary Low-Density Parity-Check Codes

Searching for good encoding and decoding schemes with excellent performance and low complexity is now a hotspot of channel coding.Low-density parity-check?LDPC?codes are such kinds of codes and have been applied to a wide range of communication domain.It has been proved that non-binary LDPC codes have better error correction performance than binary LDPC codes,especially when combined with high order modulation.The complexity of most soft decision decoding algotithems is very high,and the reliability based decoding algorithms with low complexity are mostly combined with BPSK modulation.This paper investigates the reliability based non-binary LDPC coded modulation system,proposes two kinds of bit reliability based iterative detection-decoding algorithms with QAM modulation,and makes a hardware design according to one of the proposed algorithms.The following contents are summarized as below:Firstly,the basic knowledge of non-binary LDPC codes and a non-binary LDPC coded modulation system are introduced.Decoding algorithms such as sum-product algorithm and extended min-sum algorithm are introduced.The error correction performance shows that the non-binary LDPC coded modulation system performes well with various decoding algorithms.Secondly,the reliability based non-binary LDPC decoding algorithms are introduced.On the basic of high order modulation,two kinds of iterative joint detection-decoding algorithms are proposed.Algorithm A uses the output of the decoder to update the received symbol from the channel,and proposes a new measurement of bit reliability based on decision boundary.Algorithm B uses bit log-likelihood ratio as a reliability metric,and update the bit log-likelihood ratios by the iteration between the detector and the decoder.The simulation result shows that at a BER of 10^-5,the performances of algorithm A is 0.7 dB away from algorithm B,while the decoding complexity of algorithms A is lower than algorithms B.Finally,we propose a hardware design for algorithm B.A detailed analysis of sub-modules is given based on a non-binary LDPC code over GF?16?.