Low-Complexity Decoding Algorithms And Decoder Design For Nonbinary Low-Density Parity-Check Coded-Modulation Systems

Low-density parity-check(LDPC) codes are a class of forward error correction codes which possess excellent performance in error correcting and have already been extensively studied and applied to practical communication systems. The nonbinary LDPC codes based on finite fields GF(q)(q > 2) were shown to have better error-correcting performance than their binary counterparts, especially when combined with high-order modulations. However, the high decoding complexity of nonbinary LDPC codes is hampering their application in communication systems.This thesis investigates the low-complexity decoding algorithms for nonbinary LDPC-coded modulation, as well as a hardware design according to one of nonbinary LDPC algorithm proposed in this paper. The main contents are summarized as follows:Firstly, the basic knowledge of nonbinary LDPC codes and some classic decoding algorithms including sum-product algorithm and extended min-sum algorithm are introduced. The error-correcting performance of nonbinary LDPC codes, binary LDPC codes and Turbo codes is compared.Secondly, the coded-modulation system of nonbinary LDPC codes is introduced and the simulations of this system are given. On the basis of iterative joint detection-decoding(IJDD) algorithm for the coded-modulation system, two low-complexity algorithms named improved IJDD algorithm A and improved IJDD algorithm B are developed. Of the two algorithms, algorithm A has better error-correcting performance and algorithm B is more suitable for hardware implementation.Finally, a hardware design of improved IJDD algorithm B is proposed. The structures of the decoder and its sub-modules are also given in detail.