Research On Jamming And Anti-jamming About Satellite Navigation Receiver With Array Antenna

This thesis focuses on the jamming and anti-jamming technique of GPS receiver using array antenna,searchsing its maximum possible interference tolerance and studying the methods to interference with GPS receiver high efficiently.There are two purposes to conduct indepth research from this two aspects at the same time.One is to research the array antenna technique that can be used to enhance the anti-jamming capability of the BeiDou navigation receiver,and the other is to research the jamming pattern and method that can effectively interfere with the GPS receiver.The main contents of this thesis are summarized as follows: 1.The basic principle of adaptive nulling antenna technique is studied,and the definition of interference tolerance of GPS receiver is given.The main limitation of interference tolerance is analyzed.A simulation test method of GPS receiver interference tolerance is proposed.The technical measures adopted in GPS modernization plan are studied and a new reliable and effective method to interference with modernized GPS receiver is given.2.This thesis presents an anti-jamming method of adaptive nulling antenna with beamforming.For the N-element antenna,the proposed method can obtain a SINR gain of 10log(N)dB,compared to the method of adaptive nulling antenna only.3.Aiming at the GPS receiver using array antenna,in the case of multi-source interference,the performance of Gaussian noise interference and periodic flicker interference is studied and a random flicker interference pattern is designed.The simulation results show that the random flicker interference has better interference performance than periodic flicker interference and Gaussian noise interference when the number of interference sources is less than the number of antenna elements.4.The FPGA design of the adaptive notching LMS algorithm based on floating point number in GPS receiver is completed and the correctness is verified.On the basis of this,an improved FPGA design scheme is proposed,which greatly improves the shortcoming of the convergence speed of LMS algorithm based on floating point number.