A FPGA Based Spiking Neuron Network Accelerator

With the rapid development of Internet and the rising popularity of electronic products,intelligent hardware put forward a higher request on computing power and the real-time of information processing.Compared with the computer,the biological brain works on a low frequency,which achieve a high parallel degree and a strong fault-tolerant ability and can complete all kinds of real-time tasks efficiently.In order to improve the computational efficiency of intelligent hardware,the concept of biological neural network is widely used in the design of the computer system.Spiking Neural Network(SNN)is a kind of biologically-inspired neural networks that perform information processing based on discrete-time spikes.This paper proposes a FPGA based hardware accelerator,which supports the flexible configuration of topology and synapse weights.Firstly,the paper introduces the behavior of biological neurons.We select LIF(Leaky Integrate-and-Fire,LIF)model as the basic neuronal model and optimize the mathematical model of LIF in formula by means of a floating-point turning point to suit hardware implementation on FPGA.The SNN is driven by the input events to improve the computational efficiency and reduce storage resources waste as well.Secondly,the paper introduce the hard design of SNN accelerator,including the whole hardware architecture,design of a signal neuron,pipeline design solution and classification strategy.Besides,we reorganize the architecture of memory to optimize the usage of on-chip storage resources.To ensure the the transmission of configuration data,we make a specific transport protocol.We verify the basic function of SNN by use of VCS tools.And then 8physical LIF neurons are implemented,which could be extended to 256 neurons by using time-multiplexing technology.To improve the data processing efficiency of the spiking neuron,the design adopts three-stage pipeline architecture to calculate the neuron voltage.Thirdly,the test platform for SNN accelerator is introduced,including the core OR1200,wishbone bus protocol,SPI self-start circuit and SDRAM controller.At last,MINST database is used as an application example to demonstrate the configurability and efficiency of the proposed implementation.We construct the handwritten digital recognition network architecture and use MINST data set as a test sample.The design is implemented on XC6SLX45 CSG324 FPGA running over 50 MHz operation frequency.The experimental results show the accuracy of handwritten number classification could be achieved as high as 93%.It costs 20 ns for SNN accelerator to simulate the behavior of a biological neuron and it needs 640 ns to update all the neurons in SNN,which is about 1600 times faster than the actual biological neurons in processing pulses.This SNN accelerator is slightly superior than foreign same type accelerator Minitaur in performance,which achieves expected goal basically.