Study On Non-binary LDPC Codes And The Implementations For 5G Systems

In 1963,Gallager proposed the concept of LDPC codes,together with non-binary LDPC codes based on module operation.In 1998,Davey and MacKay extended the non-binary LDPC codes to the high order of the finite field GF(q).Non-binary LDPC codes have an excellent performance over middle and short code length,while they have a limited application due to the high decoding complexity.This thesis will focus on the codes design and implementation of high speed encoder and decoder for the non-binary codes.Firstly,the message passing based iterative decoding algorithm is introduced,including Q-ary sum prod-uct algorithm(QSPA),extended min-sum(EMS)and their modification algorithms based on trellis graph.Details of these algorithms and their complexity analysis are given.Monte Carlo simulations are carried out using some constructed non-binary LDPC codes.Then,the threshold analysis method of extrinsic information transfer(EXIT)chart is introduced and the construction scheme based on protograph with quasi cyclic matrix(NB-QC-PLDPC)is presented.The relationship between the threshold and GF(q)can be observed,which provides a theoretical basis for the design of non-binary LDPC codes.The construction scheme of NB-QC-PLDPC contains the optimization of protograph structure,quasi-cyclic matrix parameters and non-binary element tuples.Finally,Monte Carlo simulations are carried out.For the ultra short code length of k=96 and code rate R= 0.5,NB-QC-PLDPC codes can achieve almost 1dB gain against Turbo codes.NB-QC-PLDPC codes also outperform than convolution codes,WiMAX,CCSDS structure LDPC codes and polar codes.Besides,longer length code and higher rate scenario is considered,NB-QC-PLDPC codes also show the outstanding performance.Then,the heterogeneous computing platform using FPGA is implemented,including the interface be-tween the FPGA and computer and high speed decoder.Firstly,the reasonableness of FPGA assisted acceler-ation is discussed from the aspect of performance and flexibility.A total 190Mbps throughput can be achieved for the implemented system.Secondly,a non-binary LDPC encoder and full parallel decoder is proposed and implemented.Encoder's key modules contains the GF(q)multiply operation and encoder procedure.For decoder,variable node unit,permutation node unit and check node unit are presented in details.Finally,the application of non-binary LDPC decoding algorithm in physical layer network coding(PLNC)system is investigated.Firstly,the system model of PLNC is given,where the combination of two users' binary LDPC codes can be treated as a non-binary LDPC code in the relay.So a generalized decoding algorithm based on the QSPA is proposed.Then,a symbol level pre-rotation scheme is proposed to combat the channel carrier asynchronous.Simulation results show that this pre-rotation scheme can take advantage of LDPC code's error correction ability and improve the robustness of the system,especially in the worst case.