The Design Of The Circuit Of 80MHz I/Q Baseband Signal Generator

The I/Q baseband signals generator is used to synthetize I/Q baseband signals according to the needs of users.It is widely used in the fields of the communication,radar,satellite for design and test.This thesis focuses on the design of the circuit.The following work have been finished.(1)Overall scheme has been designed.The I/Q baseband signals generator has been divide into I/Q signals synthesis circuit and I/Q signals adjusting circuit according to the form of the I/Q baseband signals generator.The scheme of circuit for I/Q signals synthesis based on FPGA+DDR3 SDRAM+DAC has been designed by analysing the functional modules and their realization of real time modle and arbitrary wave mode.The DDR3 SDRAM controller can be relized by user interface logic and dedicated IP core in FPGA.Symbol generator,mapping for modulation,shaping filter,interpolating filter,DDS can also be relized in FPGA,which improved the hardware integration.The scheme of I/Q signals adjusting circuit has been designed according to the characteristics of the ouput of the I/Q signals synthesis circuit,the circuit for output form transformation,reconstruction filter,amplitude control circuitand and bias circuit were include.(2)The I/Q signals synthesis circuit has been designed and realized.Oversampling was used to lower the requirement of the reconstruction filter due to the relationship between sampling rate,output bandwidth and mirror frequency.Digital analog conversion circuit was established based on AD9788 which is a DAC chip with 800 MSPS sampling rate and dual channel.Interpolation,precision controling of amplitude and phase compensation were realized in the AD9788 througth the control register.The circuit of read-write for the waveform data was established based on KVR13s9s8/4,a DDR3 SDRAM chip,according to the analysis of the requirement of speed and storage capacity in the arbitrary wave mode.The KVR13s9s8/4 realized the synthesis of arbitrary I/Q signals under the control of the FPGA.The circuit has been designed,which included Bank partition in the FPGA and pin connection between FPGA and peripheral chips according to the requirement of logical resources and t I/O pins in FPGA and Data rate,level standard,signal integrity of the AD9788 and KVR13s9s8/4.(3)The I/Q signals adjusting circuit has been designed and realized.In the transforming circuit,single ended signals were transformed to differential because the required output of the I/Q baseband signals generator is differential,while differential signals were transformed to single ended for reducing circuit redundancy.After the comparing ofr chebyshev filter,pasteur filter,bessel filter and elliptic filter,9 order elliptic filter has been designed because of the requirement of narrow transition band,large stopband attenuation and Linear phase.In consideration of the amplitude-frequency response of the multiplier is not flat enough,The circuit for amplitude fine-tuning has been realized by controlling the output current of DAC instead of multiplier.The multistage attenuation and Amplifying with fixed gain were used to realize the wide dynamic range amplitude control of the output signals.The design of I/Q baseband signals generator has been tested and verified,the results showed that it could synthesise I/Q signals with 80 MHz output bandwidth,and the EVM?1%.The output amplitude of the I/Q signals ranged frome 0.02VPP-2 VPP and the bias ranged frome-3V to +3V.